 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| mc68hc705p9/d rev. 3 mc68hc705p9 hcmos microcontroller unit technical data 68hc 5
m o t o r o l a csic microcontrollers motorola, inc., 1996 motorola 3 list of sections table of contents . . . . . . . . . . . . . . . . . . . . . . . . . 5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 13 memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 central processor unit (cpu) . . . . . . . . . . . . . . . 33 resets and interrupts. . . . . . . . . . . . . . . . . . . . . . 55 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . 65 parallel i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . 71 computer operating properly watchdog (cop) . . . . . . . . . . . . . . . . . . . . . . 85 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 serial input/output port (siop). . . . . . . . . . . . . 107 analog-to-digital converter (adc). . . . . . . . . 121 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 131 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 literature updates . . . . . . . . . . . . . . . . . . . . . . . 151 4 motorola list of sections list of modules list of modules all m68hc05 microcontroller units (mcus) are customer-specified modular designs. to meet customer requirements, motorola is constantly designing new modules and new versions of existing modules. the following table shows the version levels of the modules in the mc68hc705p9 mcu. revision history the following table summarizes differences between this revision and the previous revision of this technical data manual. module version central processor unit (cpu) hc05cpu timer tim1ic1oc_a serial input/output port (siop) siop_a computer operating properly watchdog (cop) cop0cop analog-to-digital converter (adc) atd4x8nvrl previous revision 2.0 current revision 3.0 date 11/95 changes format and organizational changes location throughout motorola table of contents 5 table of contents list of sections list of modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 introduction contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 package types and order numbers . . . . . . . . . . . . . . . . . . . . . . . . . .12 programmable options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 pin descriptions contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 input/output register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 eprom/otprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mask option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 cpu contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table of contents 6 table of contents motorola cpu control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 arithmetic/logic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 cpu registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 resets and interrupts contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 low-voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 low-power modes contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 parallel i/o ports contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 port a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 port b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 cop contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 cop register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 table of contents motorola table of contents 7 timer contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 siop contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 adc contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 timing and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . .125 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 table of contents 8 table of contents motorola specifications contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 5.0 v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .135 3.3 v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .136 driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 typical supply current vs. internal clock frequency . . . . . . . . . . . .138 maximum supply current vs. internal clock frequency . . . . . . . . . .139 5.0 v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 3.3 v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 test load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 literature updates literature distribution centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 mfax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 motorola sps world marketing world wide web server . . . . . . . . .152 csic microcontroller divisions web site . . . . . . . . . . . . . . . . . . . . .152 motorola introduction 9 introduction contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 package types and order numbers . . . . . . . . . . . . . . . . . . . . . . . . . .12 programmable options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1-mc68hc705p9 introduction features 10 introduction motorola features ? four peripheral modules C 16-bit input capture/output compare timer C synchronous serial i/o port (siop) C 4-channel, 8-bit analog-to-digital converter (adc) C computer operating properly (cop) watchdog ? 20 bidirectional i/o port pins and one input-only port pin ? on-chip oscillator with connections for: C crystal C ceramic resonator C external clock ? 2104 bytes of eprom/otprom C 48 bytes of page zero eprom/otprom C eight locations for user vectors ? 128 bytes of user ram ? bootloader rom ? memory-mapped input/output (i/o) registers ? fully static operation with no minimum clock speed ? power-saving stop, wait, and data-retention modes 2-mc68hc705p9 introduction structure motorola introduction 11 structure figure 1. mc68hc705p9 block diagram 0000011 cpu control arithmetic/logic unit accumulator index register stack pointer program counter 00 m68hc05 mcu reset condition code register 111hi ncz data direction register a port a pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 internal oscillator divide by 2 irq/v pp v dd v ss osc1 osc2 bootloader rom 240 bytes ram 128 bytes reset 0 port b pb7/sck pb6/sdi pb5/sdo data direction register c port c eprom/otprom 2104 bytes pc7/v rh pc6/an0 pc5/an1 pc4/an2 pc3/an3 pc2 pc1 pc0 an1 an2 an3 adc cpu clock power internal clock 0 0 0 cop watchdog to adc and siop divide by 4 an0 v rh sdi sdo siop sck data direction register b port d data direction register d capture/compare timer pd5 pd7/tcap tcap tcmp 3-mc68hc705p9 introduction package types and order numbers 12 introduction motorola package types and order numbers programmable options 1. dip = dual in-line package 2. soic = small outline integrated circuit 3. cerdip = ceramic dip the options in table 2 are programmable in the mask option register. table 1. order numbers package type case outline pin count operating temperature order number plastic dip (1) 710 28 0 to +70 c C40 to +85 c C40 to +105 c C40 to +125 c mc68hc705p9p mc68hc705p9cp mc68hc705p9vp mc68hc705p9mp soic (2) 733 28 0 to +70 c C40 to +85 c C40 to +105 c C40 to +125 c mc68hc705p9dw mc68hc705p9cdw MC68HC705P9VDW mc68hc705p9mdw cerdip (3) 751f 28 0 to +70 c C40 to +85 c C40 to +105 c C40 to +125 c mc68hc705p9s mc68hc705p9cs mc68hc705p9vs mc68hc705p9ms table 2. programmable options feature option cop watchdog enabled or disabled external interrupt pin triggering negative-edge triggering only or negative-edge and low-level triggering siop data format msb first or lsb first 4-mc68hc705p9 motorola pin descriptions 13 pin descriptions contents pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 v dd and v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 osc1 and osc2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 crystal connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 ceramic resonator connections . . . . . . . . . . . . . . . . . . . . . . . .16 external clock connections . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 irq/v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 pa7Cpa0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 pb7/sckCpb5/sdo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 pc7/v rh Cpc0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 pd7/tcap and pd5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 tcmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1-mc68hc705p9 pin descriptions pin assignments 14 pin descriptions motorola pin assignments figure 1. pin assignments reset irq /v pp pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 pb5/sdo pb6/sdi pb7/sck v ss v dd osc1 osc2 pd7/tcap tcmp pd5 pc0 pc1 pc2 pc3/an3 pc4/an2 pc5/an1 pc6/an0 pc7/v rh 2-mc68hc705p9 pin descriptions pin functions motorola pin descriptions 15 pin functions v dd and v ss v dd and v ss are the power supply and ground pins. the mcu operates from a single 5-v power supply. very fast signal transitions occur on the mcu pins, placing high short-duration current demands on the power supply. to prevent noise problems, take special care to provide good power supply bypassing at the mcu as figure 2 shows. place the bypass capacitors as close as possible to the mcu. c2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. osc1 and osc2 the osc1 and osc2 pins are the connections for the on-chip oscillator. the oscillator can be driven by any of the following: ? crystal ? ceramic resonator ? external clock signal the frequency of the on-chip oscillator is f osc . the mcu divides the internal oscillator output by two to produce the internal clock with a frequency of f op . mcu v dd v ss c1 0.1 m f c2 v dd + figure 2. bypassing recommendation 3-mc68hc705p9 pin descriptions pin functions 16 pin descriptions motorola crystal connections the circuit in figure 3 shows a typical crystal oscillator circuit for an at-cut, parallel resonant crystal. follow the crystal suppliers recommendations, as the crystal parameters determine the external component values required to provide reliable startup and maximum stability. the load capacitance values used in the oscillator circuit design should include all stray layout capacitances. to minimize output distortion, mount the crystal and capacitors as close as possible to the pins. note: use an at-cut crystal. do not use a strip or tuning fork crystal. the mcu may overdrive or have the incorrect characteristic impedance for a strip or tuning fork crystal. ceramic resonator connections to reduce cost, use a ceramic resonator in place of the crystal. figure 4 shows a ceramic resonator circuit. for the values of any external components, follow the recommendations of the resonator manufacturer. the load capacitance values used in the oscillator circuit design should include all stray layout capacitances. to minimize output distortion, mount the resonator and capacitors as close as possible to the pins. mcu osc1 osc2 xtal 10 m w ? 27 pf 27 pf figure 3. crystal connections mcu osc1 osc2 ceramic resonator figure 4. ceramic resonator connections 4-mc68hc705p9 pin descriptions pin functions motorola pin descriptions 17 note: because the frequency stability of ceramic resonators is not as high as that of crystal oscillators, using a ceramic resonator may degrade the performance of the adc. external clock connections an external clock from another cmos-compatible device can drive the osc1 input, with the osc2 pin unconnected, as figure 5 shows. reset a logic zero on the reset pin forces the mcu to a known startup state. the reset pin input circuit contains an internal schmitt trigger to improve noise immunity. irq /v pp the irq/v pp pin has the following functions: ? applying asynchronous external interrupt signals ? applying v pp , the eprom/otprom programming voltage pa7Cpa0 pa7Cpa0 are general-purpose bidirectional i/o port pins. use data direction register a to configure port a pins as inputs or outputs. pb7/sckC pb5/sdo port b is a 3-pin bidirectional i/o port that shares its pins with the siop. use data direction register b to configure port b pins as inputs or outputs. pc7/v rh Cpc0 port c is an 8-pin bidirectional i/o port that shares five of its pins with the adc. use data direction register c to configure port c pins as inputs or outputs. mcu osc1 osc2 external cmos clock unconnected figure 5. external clock connections 5-mc68hc705p9 pin descriptions pin functions 18 pin descriptions motorola pd7/tcap and pd5 port d is a 2-pin i/o port that shares one of its pins with the capture/compare timer. use data direction register d to configure port d pins as inputs or outputs. tcmp the tcmp pin is the output compare pin for the capture/compare timer. 6-mc68hc705p9 motorola memory 19 1-mc68hc705p9 memory contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 input/output register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 ram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 eprom/otprom. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 eprom/otprom programming . . . . . . . . . . . . . . . . . . . . . . . . . .26 eprom programming register . . . . . . . . . . . . . . . . . . . . . . . . .26 bootloader rom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 eprom erasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 mask option register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 features ? 2104 bytes of eprom/otprom C 48 bytes of page zero eprom/otprom C eight locations for user vectors ? 128 bytes of user ram ? bootloader rom memory memory map 20 memory motorola memory map $0000 $001f i/o registers (32 bytes) port a data register (porta) $0000 port b data register (portb) $0001 port c data register (portc) $0002 $0020 $004f page zero user eprom (48 bytes) port d data register (portd) $0003 data direction register a (ddra) $0004 data direction register b (ddrb) $0005 $0050 $007f unimplemented (48 bytes) data direction register c (ddrc) $0006 data direction register d (ddrd) $0007 unimplemented $0008 $0080 $00ff ram (128 bytes) $0009 siop control register (scr) $000a siop status register (ssr) $000b $0100 $08ff user eprom (2048 bytes) siop data register (sdr) $000c unimplemented $000d $000e $0900 mask option register $000f $0901 $1eff unimplemented (5631 bytes) $0010 $0011 timer control register (tcr) $0012 $1f00 $1fef bootloader rom (240 bytes) timer status register (tsr) $0013 input capture register high (icrh) $0014 input capture register low (icrl) $0015 $1ff0 cop control register output compare register high (ocrh) $0016 $1ff1 $1ff7 reserved output compare register low (ocrl) $0017 timer register high (trh) $0018 timer register low (trl) $0019 $1ff8 $1fff user vector eprom (8 bytes) alternate timer register high (atrh) $001a alternate timer register low (atrl) $001b eprom programming register (eprog) $001c adc data register (addr) $001d adc status/control register (adscr) $001e reserved $001f timer interrupt vector high $1ff8 timer interrupt vector low $1ff9 external interrupt vector high $1ffa external interrupt vector low $1ffb software interrupt vector high $1ffc software interrupt vector low $1ffd reset vector high $1ffe reset vector low $1fff figure 1. memory map 2-mc68hc705p9 memory input/output register summary motorola memory 21 3-mc68hc705p9 input/output register summary addr. name r/w bit 7 654321 bit 0 $0000 port a data register (porta) read: pa 7 pa 6 pa 5 pa 4 pa 3 pa 2 pa 1 pa 0 write: reset: unaffected by reset $0001 port b data register (portb) read: pb7 pb6 pb5 00000 write: reset: unaffected by reset $0002 port c data register (portc) read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: unaffected by reset $0003 port d data register (portd) read: pd7 0 pd5 10000 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 00000 write: reset: 00000000 $0006 data direction register c (ddrc) read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 00000000 $0007 data direction register d (ddrd) read: 00 ddrd5 00000 write: reset: 00000000 $0008 unimplemented $0009 unimplemented = unimplemented r = reserved u = unaffected figure 2. i/o register summary memory input/output register summary 22 memory motorola $000a siop control register (scr) read: 0 spe 0 mstr 0000 write: reset: 00000000 $000b siop status register (ssr) read: spif dcol 000000 write: reset: 00000000 $000c siop data register (sdr) read: bit 7 654321 bit 0 write: reset: unaffected by reset $000d unimplemented $000e unimplemented $000f unimplemented $0010 unimplemented $0011 unimplemented $0012 timer control register (tcr) read: icie ocie toie 0 0 0 iedg olvl write: reset: 000000u0 $0013 timer status register (tsr) read: icfocftof00000 write: reset: unaffected by reset 00000 $0014 input capture register high (icrh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: $0015 input capture register low (icrl) read: bit 7 654321 bit 0 write: reset: unaffected by reset $0016 output compare register high (ocrh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: unaffected by reset addr. name r/w bit 7 654321 bit 0 = unimplemented r = reserved u = unaffected figure 2. i/o register summary (continued) 4-mc68hc705p9 memory input/output register summary motorola memory 23 $0017 output compare register low (ocrl) read: bit 7 654321 bit 0 write: reset: unaffected by reset $0018 timer register high (trh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: reset initializes trh to $ff $0019 timer register low (trl) read: bit 7 654321 bit 0 write: reset: reset initializes trl to $fc $001a alternate timer register high (atrh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: reset initializes atrh to $ff $001b alternate timer register low (atrl) read: bit 7 654321 bit 0 write: reset: reset initializes atrl to $fc $001c eprom programming register (eprog) read: 00000 latch 0 epgm write: rrrrr r reset: unaffected by reset $001d adc data register (addr) read: bit 7 654321 bit 0 write: reset: unaffected by reset $001e adc status/control register (adscr) read: ccf adrc adon 00 ch2 ch1 ch0 write: reset: 00000000 $001f reserved read: rrrrrrrr write: reset: addr. name r/w bit 7 654321 bit 0 = unimplemented r = reserved u = unaffected figure 2. i/o register summary (continued) 5-mc68hc705p9 memory ram 24 memory motorola ram the 128 addresses from $0080C$00ff are ram locations. the cpu uses the top 64 ram addresses, $00c0C$00ff, as the stack. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements when the cpu stores a byte on the stack and increments when the cpu retrieves a byte from the stack. note: be careful when using nested subroutines or multiple interrupt levels. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. $0900 mask option register (mor) read: 00000 siop irq cope write: reset: unaffected by reset 0 $1ff0 cop register (copr) read: rrrrrrr copc write: reset: unaffected by reset addr. name r/w bit 7 654321 bit 0 = unimplemented r = reserved u = unaffected figure 2. i/o register summary (continued) 6-mc68hc705p9 memory eprom/otprom motorola memory 25 eprom/otprom an mcu with a quartz window has 2104 bytes of erasable, programmable rom (eprom). the quartz window allows eprom erasure with ultraviolet light. note: keep the quartz window covered with an opaque material except when programming the mcu. ambient light may affect mcu operation. in an mcu without the quartz window, the eprom cannot be erased and serves as 2104 bytes of one-time programmable rom (otprom). the following addresses are user eprom/otprom locations: ? $0020C$004f ? $0100C$08ff ? $1ff8C$1fff (reserved for user-defined interrupt and reset vectors) the mask option register (mor) is an eprom/otprom location at address $0900. 7-mc68hc705p9 memory eprom/otprom 26 memory motorola eprom/ otprom programming the two ways to program the eprom/otprom are: ? manipulating the control bits in the eprom programming register to program the eprom/otprom on a byte-by-byte basis ? activating the bootloader rom to download the contents of an external memory device to the on-chip eprom/otprom eprom programming register the eprom programming register contains the control bits for programming the eprom/otprom. latch eprom bus latch this read/write bit latches the address and data buses for eprom/otprom programming. clearing the latch bit automatically clears the epgm bit. eprom/otprom data cannot be read while the latch bit is set. resets clear the latch bit. 1 = address and data buses configured for eprom/otprom programming 0 = address and data buses configured for normal operation epgm bit eprom programming this read/write bit applies the voltage from the irq/v pp pin to the eprom/otprom. to write the epgm bit, the latch bit must already be set. clearing the latch bit also clears the epgm bit. resets clear the epgm bit. 1 = eprom/otprom programming power switched on 0 = eprom/otprom programming power switched off $001c bit 7 654321 bit 0 read: 00000 latch 0 epgm write: rrrrr r reset: 00000000 r = reserved figure 3. eprom programming register (eprog) 8-mc68hc705p9 memory eprom/otprom motorola memory 27 note: writing logic ones to both the latch and epgm bits with a single instruction sets latch and clears epgm. latch must be set first by a separate instruction. bits 7C3 and bit 1 reserved bits 7C3 and bit 1 are factory test bits that always read as logic zeros. take the following steps to program a byte of eprom/otprom: 1. apply 16.5 v to the irq/v pp pin. 2. set the latch bit. 3. write to any eprom/otprom address. 4. set the epgm bit for a time, t epgm , to apply the programming voltage. 5. clear the latch bit. bootloader rom the bootloader rom, located at addresses $1f00C$1fef, contains routines for copying an external eprom to the on-chip eprom/otprom. the bootloader copies to the following eprom/otprom addresses: ? $0020C$004f ? $0100C$0900 ? $1ff0C$1fff the addresses of the code in the external eprom must match the mc68hc705p9 addresses. the bootloader ignores all other addresses. figure 4 shows the circuit for downloading to the on-chip eprom/otprom from a 2764 eprom. the bootloader circuit includes an external 12-bit counter to address the external eprom. operation is fastest when unused external eprom addresses contain $00. the bootloader function begins when a rising edge occurs on the resetpin while the v pp voltage is on the irq/v pp pin, and the pd7/tcap pin is at logic one. 9-mc68hc705p9 memory eprom/otprom 28 memory motorola figure 4. bootloader circuit q1 q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 rst clk d0 d1 d2 d3 d4 d5 d6 d7 ce oe a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 irq/v pp osc1 osc2 pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 reset mc68hc705p9 2764 v dd pc5/an1 pc6/an0 program verify v dd 1 m f pb7/sck pb6/sdi 10 k w s2 s3 v dd v dd 10 k w s1 10 k w 2 mhz v pp mc14040b 330 w 330 w 10 m w 10 k w pb5 pd7 pc1 pc2 pc4 pc3 2 27 26 10 9 8 7 6 5 4 3 11 25 21 20 18 19 1 17 16 13 12 10-mc68hc705p9 memory eprom/otprom motorola memory 29 the logical states of the pc4/an2 and pc3/an3 pins select the bootloader function, as table 1 shows. complete the following steps to bootload the mcu: 1. turn off all power to the circuit. 2. install the eprom containing the code to be downloaded. 3. install the mcu. 4. select the bootloader function: a. open switches s2 and s3 to select the program and verify function. b. open only switch s2 to select only the verify function. 5. close switch s1. 6. turn on the v dd power supply. caution: turn on the v dd power supply before turning on the v pp power supply. 7. turn on the v pp power supply. 8. open switch s1. the bootloader code begins to execute. if the program function is selected, the program led turns on during programming. if the verify function is selected, the verify led turns on when verification is successful. the program and verify functions take about 10 seconds. 9. close switch s1. 10. turn off the v pp power supply. table 1. bootloader function selection pc4/an2 pc3/an3 function 1 1 program and verify 1 0 verify only 11-mc68hc705p9 memory eprom/otprom 30 memory motorola caution: turn off the v pp power supply before turning off the v dd power supply. 11. turn off the v dd power supply. eprom erasing the erased state of an eprom bit is zero. erase the eprom by exposing it to 15 ws/cm 2 of ultraviolet light with a wavelength of 2537 angstroms. position the ultraviolet light source one inch from the eprom. do not use a shortwave filter. cerdip packages have a transparent window for erasing the eprom with ultraviolet light. in the windowless pdip and soic packages, the 2104 eprom bytes function as one-time programmable rom (otprom). 12-mc68hc705p9 memory mask option register motorola memory 31 mask option register the mask option register (mor) is an eprom/otprom byte that is programmable only with the bootloader function. the mor controls the following options: ? lsb first or msb first siop data transfer ? edge-triggered or edge- and level-triggered external interrupt pin ? enabled or disabled cop watchdog to program the mor, use the 5-step procedure given in the section eprom programming register on page 26. write to address $0900 in step 3. siop serial i/o port the siop bit controls the shift direction into and out of the siop shift register. 1 = siop data transferred lsb first (bit 0 first) 0 = siop data transferred msb first (bit 7 first) irq interrupt request the irq bit makes the external interrupt function of the irq/v pp pin level-triggered as well as edge-triggered. 1 = irq/v pp pin negative-edge triggered and low-level triggered 0 = irq/v pp pin negative-edge triggered only $0900 bit 7 654321 bit 0 read: 00000 siop irq cope write: reset: unaffected by reset erased: 00000000 = unimplemented figure 5. mask option register (mor) 13-mc68hc705p9 memory mask option register 32 memory motorola cope cop enable cope enables the cop watchdog. in applications that have wait cycles longer than the cop watchdog timeout period, the cop watchdog can be disabled by not programming the cope bit to logic one. 1 = cop watchdog enabled 0 = cop watchdog disabled 14-mc68hc705p9 motorola cpu 33 central processor unit cpu contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 cpu control unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 arithmetic/logic unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 cpu registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 program counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 indexed, no offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 indexed, 8-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 indexed, 16-bit offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 instruction types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 register/memory instructions . . . . . . . . . . . . . . . . . . . . . . . . . .43 read-modify-write instructions . . . . . . . . . . . . . . . . . . . . . . . . .44 jump/branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 bit manipulation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . .47 control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 1-hc05cpu cpu features 34 cpu motorola features ? 2.1-mhz bus frequency ? 8-bit accumulator ? 8-bit index register ? 13-bit program counter ? 6-bit stack pointer ? condition code register with five status flags ? 62 instructions ? eight addressing modes ? power-saving stop, wait, and data-retention modes introduction the central processor unit (cpu) consists of a cpu control unit, an arithmetic/logic unit (alu), and five cpu registers. the cpu control unit fetches and decodes instructions. the alu executes the instructions. the cpu registers contain data, addresses, and status bits that reflect the results of cpu operations. 2-hc05cpu cpu introduction motorola cpu 35 figure 1. cpu programming model accumulator (a) index register (x) condition code register (ccr) program counter (pc) stack pointer (sp) half-carry flag interrupt mask negative flag zero flag carry/borrow flag 0 4 75 6 321 0 arithmetic/logic unit cpu control unit 0 4 75 6 321 0 4 75 6321 8 12 15 13 14 11 10 9 000000011 0 00 0 4 75 6321 8 12 15 13 14 11 10 9 111hinzc 0 4 75 6321 3-hc05cpu cpu cpu control unit 36 cpu motorola cpu control unit the cpu control unit fetches and decodes instructions during program operation. the control unit selects the memory locations to read and write and coordinates the timing of all cpu operations. arithmetic/logic unit the arithmetic/logic unit (alu) performs the arithmetic, logic, and manipulation operations decoded from the instruction set by the cpu control unit. the alu produces the results called for by the program and sets or clears status and control bits in the condition code register (ccr). cpu registers the m68hc05 cpu contains five registers that control and monitor mcu operation: ? accumulator ? index register ? stack pointer ? program counter ? condition code register cpu registers are not memory mapped. 4-hc05cpu cpu cpu registers motorola cpu 37 accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic and logic operations. index register the index register can be used for data storage or as a counter. in the indexed addressing modes, the cpu uses the byte in the index register to determine the effective address of the operand. stack pointer the stack pointer is a 16-bit register that contains the address of the next stack location to be used. during a reset or after the reset stack pointer instruction (rsp), the stack pointer is preset to $00ff. the address in the stack pointer decrements after a byte is stacked and increments before a byte is unstacked. bit 7 654321 bit 0 read: write: reset: unaffected by reset figure 2. accumulator (a) bit 7 654321 bit 0 read: write: reset: unaffected by reset figure 3. index register (x) bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: 0 0 0 0 0 0 0 0 1 1 write: reset: 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 = unimplemented figure 4. stack pointer (sp) 5-hc05cpu cpu cpu registers 38 cpu motorola the 10 most significant bits of the stack pointer are permanently fixed at 0000000011, so the stack pointer produces addresses from $00c0 to $00ff. if subroutines and interrupts use more than 64 stack locations, the stack pointer wraps around to address $00ff and begins writing over the previously stored data. a subroutine uses two stack locations; an interrupt uses five locations. program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. the three most significant bits of the program counter are ignored internally and appear as 000. normally, the address in the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. condition code register the condition code register is an 8-bit register whose three most significant bits are permanently fixed at 111. the condition code register contains the interrupt mask and four flags that indicate the results of the instruction just executed. bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 bit 0 read: write: reset: 0 0 0 loaded with vector from $1ffe and $1fff figure 5. program counter (pc) bit 7 654321 bit 0 read: 1 1 1 hinzc write: reset: 1 1 1u1uuu = unimplemented u = unaffected figure 6. condition code register (ccr) 6-hc05cpu cpu cpu registers motorola cpu 39 h half-carry flag the cpu sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during an add or adc operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. i interrupt mask setting the interrupt mask disables interrupts. if an interrupt request occurs while the interrupt mask is logic zero, the cpu saves the cpu registers on the stack, sets the interrupt mask, and then fetches the interrupt vector. if an interrupt request occurs while the interrupt mask is set, the interrupt request is latched. normally, the cpu processes the latched interrupt as soon as the interrupt mask is cleared again. a return from interrupt (rti) instruction pulls the cpu registers from the stack, restoring the interrupt mask to its cleared state. after any reset, the interrupt mask is set and can be cleared only by a software instruction. n negative flag the cpu sets the negative flag when an arithmetic operation, logical operation, or data manipulation produces a negative result. z zero flag the cpu sets the zero flag when an arithmetic operation, logical operation, or data manipulation produces a result of $00. c carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borrow flag. 7-hc05cpu cpu instruction set 40 cpu motorola instruction set the mcu instruction set has 62 instructions and uses eight addressing modes. the instructions include all those of the m146805 cmos family plus one more: the unsigned multiply (mul) instruction. the mul instruction allows unsigned multiplication of the contents of the accumulator (a) and the index register (x). the high-order product is stored in the index register, and the low-order product is stored in the accumulator. addressing modes the cpu uses eight addressing modes for flexibility in accessing data. the addressing modes provide eight different ways for the cpu to find the data required to execute an instruction. the eight addressing modes are: ? inherent ? immediate ? direct ? extended ? indexed, no offset ? indexed, 8-bit offset ? indexed, 16-bit offset ? relative inherent inherent instructions are those that have no operand, such as return from interrupt (rti) and stop (stop). some of the inherent instructions act on data in the cpu registers, such as set carry flag (sec) and increment accumulator (inca). inherent instructions require no operand address and are one byte long. immediate immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. immediate instructions require no operand address and are two bytes long. the opcode is the first byte, and the immediate data value is the second byte. 8-hc05cpu cpu instruction set motorola cpu 41 direct direct instructions can access any of the first 256 memory locations with two bytes. the first byte is the opcode, and the second is the low byte of the operand address. in direct addressing, the cpu automatically uses $00 as the high byte of the operand address. extended extended instructions use three bytes and can access any address in memory. the first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. when using the motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. the assembler automatically selects the shortest form of the instruction. indexed, no offset indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. the index register contains the low byte of the effective address of the operand. the cpu automatically uses $00 as the high byte, so these instructions can address locations $0000C$00ff. indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used ram or i/o location. indexed, 8-bit offset indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. the cpu adds the unsigned byte in the index register to the unsigned byte following the opcode. the sum is the effective address of the operand. these instructions can access locations $0000C$01fe. indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. the table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01fe). the k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. 9-hc05cpu cpu instruction set 42 cpu motorola indexed, 16-bit offset indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. the cpu adds the unsigned byte in the index register to the two unsigned bytes following the opcode. the sum is the effective address of the operand. the first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. as with direct and extended addressing, the motorola assembler determines the shortest form of indexed addressing. relative relative addressing is only for branch instructions. if the branch condition is true, the cpu finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. if the branch condition is not true, the cpu goes to the next instruction. the offset is a signed, twos complement byte that gives a branching range of C128 to +127 bytes from the address of the next location after the branch instruction. when using the motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. 10-hc05cpu cpu instruction set motorola cpu 43 instruction types the mcu instructions fall into the following five categories: ? register/memory instructions ? read-modify-write instructions ? jump/branch instructions ? bit manipulation instructions ? control instructions register/ memory instructions these instructions operate on cpu registers and memory locations. most of them use two operands. one operand is in either the accumulator or the index register. the cpu finds the other operand in memory. table 1. register/memory instructions instruction mnemonic add memory byte and carry bit to accumulator adc add memory byte to accumulator add and memory byte with accumulator and bit test accumulator bit compare accumulator cmp compare index register with memory byte cpx exclusive or accumulator with memory byte eor load accumulator with memory byte lda load index register with memory byte ldx multiply mul or accumulator with memory byte ora subtract memory byte and carry bit from accumulator sbc store accumulator in memory sta store index register in memory stx subtract memory byte from accumulator sub 11-hc05cpu cpu instruction set 44 cpu motorola read-modify- write instructions these instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. note: do not use read-modify-write operations on write-only registers. 1. unlike other read-modify-write instructions, bclr and bset use only direct addressing. 2. tst is an exception to the read-modify-write sequence be- cause it does not write a replacement value. table 2. read-modify-write instructions instruction mnemonic arithmetic shift left (same as lsl) asl arithmetic shift right asr bit clear bclr (1) bit set bset (1) clear register clr complement (ones complement) com decrement dec increment inc logical shift left (same as asl) lsl logical shift right lsr negate (twos complement) neg rotate left through carry bit rol rotate right through carry bit ror test for negative or zero tst (2) 12-hc05cpu cpu instruction set motorola cpu 45 jump/branch instructions jump instructions allow the cpu to interrupt the normal sequence of the program counter. the unconditional jump instruction (jmp) and the jump-to-subroutine instruction (jsr) have no register operand. branch instructions allow the cpu to interrupt the normal sequence of the program counter when a test condition is met. if the test condition is not met, the branch is not performed. the brclr and brset instructions cause a branch based on the state of any readable bit in the first 256 memory locations. these 3-byte instructions use a combination of direct addressing and relative addressing. the direct address of the byte to be tested is in the byte following the opcode. the third byte is the signed offset byte. the cpu finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. the bit to be tested and its condition (set or clear) is part of the opcode. the span of branching is from C128 to +127 from the address of the next location after the branch instruction. the cpu also transfers the tested bit to the carry/borrow bit of the condition code register. 13-hc05cpu cpu instruction set 46 cpu motorola table 3. jump and branch instructions instruction mnemonic branch if carry bit clear bcc branch if carry bit set bcs branch if equal beq branch if half-carry bit clear bhcc branch if half-carry bit set bhcs branch if higher bhi branch if higher or same bhs branch if irq pin high bih branch if irq pin low bil branch if lower blo branch if lower or same bls branch if interrupt mask clear bmc branch if minus bmi branch if interrupt mask set bms branch if not equal bne branch if plus bpl branch always bra branch if bit clear brclr branch never brn branch if bit set brset branch to subroutine bsr unconditional jump jmp jump to subroutine jsr 14-hc05cpu cpu instruction set motorola cpu 47 bit manipulation instructions the cpu can set or clear any writable bit in the first 256 bytes of memory, which includes i/o registers and on-chip ram locations. the cpu can also test and branch based on the state of any bit in any of the first 256 memory locations. control instructions these instructions act on cpu registers and control cpu operation during program execution. table 4. bit manipulation instructions instruction mnemonic bit clear bclr branch if bit clear brclr branch if bit set brset bit set bset table 5. control instructions instruction mnemonic clear carry bit clc clear interrupt mask cli no operation nop reset stack pointer rsp return from interrupt rti return from subroutine rts set carry bit sec set interrupt mask sei stop oscillator and enable irq pin stop software interrupt swi transfer accumulator to index register tax transfer index register to accumulator txa stop cpu clock and enable interrupts wait 15-hc05cpu cpu instruction set 48 cpu motorola instruction set summary table 6. instruction set summary source form operation description effect on ccr address mode opcode operand cycles hinzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x add with carry a ? (a) + (m) + (c) imm dir ext ix2 ix1 ix a9 b9 c9 d9 e9 f9 ii dd hh ll ee ff ff 2 3 4 5 4 3 add # opr add opr add opr add opr ,x add opr ,x add ,x add without carry a ? (a) + (m) imm dir ext ix2 ix1 ix ab bb cb db eb fb ii dd hh ll ee ff ff 2 3 4 5 4 3 and # opr and opr an d opr and opr ,x and opr ,x and ,x logical and a ? (a) (m) imm dir ext ix2 ix1 ix a4 b4 c4 d4 e4 f4 ii dd hh ll ee ff ff 2 3 4 5 4 3 asl opr asla aslx asl opr ,x asl ,x arithmetic shift left (same as lsl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 asr opr asra asrx asr opr ,x asr ,x arithmetic shift right dir inh inh ix1 ix 37 47 57 67 77 dd ff 5 3 3 6 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bclr n opr clear bit n mn ? 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? z = 1 rel 27 rr 3 bhcc rel branch if half-carry bit clear pc ? (pc) + 2 + rel ? h = 0 rel 28 rr 3 bhcs rel branch if half-carry bit set pc ? (pc) + 2 + rel ? h = 1 rel 29 rr 3 c b0 b7 0 b0 b7 c 16-hc05cpu cpu instruction set motorola cpu 49 bhi rel branch if higher pc ? (pc) + 2 + rel ? c z = 0 rel 22 rr 3 bhs rel branch if higher or same pc ? (pc) + 2 + rel ? c = 0 rel 24 rr 3 bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit test accumulator with memory byte (a) (m) imm dir ext ix2 ix1 ix a5 b5 c5 d5 e5 f5 ii dd hh ll ee ff ff 2 3 4 5 4 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? c = 1 rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? c z = 1 rel 23 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? i = 0 rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? n = 1 rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? i = 1 rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? z = 0 rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? n = 0 rel 2a rr 3 bra rel branch always pc ? (pc) + 2 + rel ? 1 = 1 rel 20 rr 3 brclr n opr rel branch if bit n clear pc ? (pc) + 2 + rel ? mn = 0 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 + rel ? 1 = 0 rel 21 rr 3 brset n opr rel branch if bit n set pc ? (pc) + 2 + rel ? mn = 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n opr set bit n mn ? 1 dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 5 5 5 5 5 5 5 5 table 6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc 17-hc05cpu cpu instruction set 50 cpu motorola bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1 pc ? (pc) + rel rel ad rr 6 clc clear carry bit c ? 0 0 inh 98 2 cli clear interrupt mask i ? 0 0 inh 9a 2 clr opr clra clrx clr opr ,x clr ,x clear byte m ? $00 a ? $00 x ? $00 m ? $00 m ? $00 0 1 dir inh inh ix1 ix 3f 4f 5f 6f 7f dd ff 5 3 3 6 5 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x compare accumulator with memory byte (a) C (m) imm dir ext ix2 ix1 ix a1 b1 c1 d1 e1 f1 ii dd hh ll ee ff ff 2 3 4 5 4 3 com opr coma comx com opr ,x com ,x complement byte (ones complement) m ? ( m) = $ff C (m) a ? ( a) = $ff C (a) x ? ( x) = $ff C (x) m ? ( m) = $ff C (m) m ? ( m) = $ff C (m) 1 dir inh inh ix1 ix 33 43 53 63 73 dd ff 5 3 3 6 5 cpx # opr cpx opr cpx opr cpx opr ,x cpx opr ,x cpx ,x compare index register with memory byte (x) C (m) imm dir ext ix2 ix1 ix a3 b3 c3 d3 e3 f3 ii dd hh ll ee ff ff 2 3 4 5 4 3 dec opr deca decx dec opr ,x dec ,x decrement byte m ? (m) C 1 a ? (a) C 1 x ? (x) C 1 m ? (m) C 1 m ? (m) C 1 dir inh inh ix1 ix 3a 4a 5a 6a 7a dd ff 5 3 3 6 5 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x exclusive or accumulator with memory byte a ? (a) ? (m) imm dir ext ix2 ix1 ix a8 b8 c8 d8 e8 f8 ii dd hh ll ee ff ff 2 3 4 5 4 3 inc opr inca incx inc opr ,x inc ,x increment byte m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 dir inh inh ix1 ix 3c 4c 5c 6c 7c dd ff 5 3 3 6 5 table 6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc 18-hc05cpu cpu instruction set motorola cpu 51 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x unconditional jump pc ? jump address dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n (n = 1, 2, or 3) push (pcl); sp ? (sp) C 1 push (pch); sp ? (sp) C 1 pc ? effective address dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 5 6 7 6 5 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x load accumulator with memory byte a ? (m) imm dir ext ix2 ix1 ix a6 b6 c6 d6 e6 f6 ii dd hh ll ee ff ff 2 3 4 5 4 3 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x load index register with memory byte x ? (m) imm dir ext ix2 ix1 ix ae be ce de ee fe ii dd hh ll ee ff ff 2 3 4 5 4 3 lsl opr lsla lslx lsl opr ,x lsl ,x logical shift left (same as asl) dir inh inh ix1 ix 38 48 58 68 78 dd ff 5 3 3 6 5 lsr opr lsra lsrx lsr opr ,x lsr ,x logical shift right 0 dir inh inh ix1 ix 34 44 54 64 74 dd ff 5 3 3 6 5 mul unsigned multiply x : a ? (x) (a) 0 0 inh 42 11 neg opr nega negx neg opr ,x neg ,x negate byte (twos complement) m ? C(m) = $00 C (m) a ? C(a) = $00 C (a) x ? C(x) = $00 C (x) m ? C(m) = $00 C (m) m ? C(m) = $00 C (m) dir inh inh ix1 ix 30 40 50 60 70 dd ff 5 3 3 6 5 nop no operation inh 9d 2 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x logical or accumulator with memory a ? (a) (m) imm dir ext ix2 ix1 ix aa ba ca da ea fa ii dd hh ll ee ff ff 2 3 4 5 4 3 table 6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 0 b0 b7 c 0 19-hc05cpu cpu instruction set 52 cpu motorola rol opr rola rolx rol opr ,x rol ,x rotate byte left through carry bit dir inh inh ix1 ix 39 49 59 69 79 dd ff 5 3 3 6 5 ror opr rora rorx ror opr ,x ror ,x rotate byte right through carry bit dir inh inh ix1 ix 36 46 56 66 76 dd ff 5 3 3 6 5 rsp reset stack pointer sp ? $00ff inh 9c 2 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 9 rts return from subroutine sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 81 6 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x subtract memory byte and carry bit from accumulator a ? (a) C (m) C (c) imm dir ext ix2 ix1 ix a2 b2 c2 d2 e2 f2 ii dd hh ll ee ff ff 2 3 4 5 4 3 sec set carry bit c ? 1 1 inh 99 2 sei set interrupt mask i ? 1 1 inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x store accumulator in memory m ? (a) dir ext ix2 ix1 ix b7 c7 d7 e7 f7 dd hh ll ee ff ff 4 5 6 5 4 stop stop oscillator and enable irq pin 0 inh 8e 2 stx opr stx opr stx opr ,x stx opr ,x stx ,x store index register in memory m ? (x) dir ext ix2 ix1 ix bf cf df ef ff dd hh ll ee ff ff 4 5 6 5 4 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x subtract memory byte from accumulator a ? (a) C (m) imm dir ext ix2 ix1 ix a0 b0 c0 d0 e0 f0 ii dd hh ll ee ff ff 2 3 4 5 4 3 table 6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc c b0 b7 b0 b7 c 20-hc05cpu cpu instruction set motorola cpu 53 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1; push (x) sp ? (sp) C 1; push (a) sp ? (sp) C 1; push (ccr) sp ? (sp) C 1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte 1 inh 83 10 tax transfer accumulator to index register x ? (a) inh 97 2 tst opr tsta tstx tst opr ,x tst ,x test memory byte for negative or zero (m) C $00 dir inh inh ix1 ix 3d 4d 5d 6d 7d dd ff 4 3 3 5 4 txa transfer index register to accumulator a ? (x) inh 9f 2 wait stop cpu clock and enable interrupts 0 inh 8f 2 a accumulator opr operand (one or two bytes) c carry/borrow ?ag pc program counter ccr condition code register pch program counter high byte dd direct address of operand pcl program counter low byte dd rr direct address of operand and relative offset of branch instruction rel relative addressing mode dir direct addressing mode rel relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing rr relative program counter offset byte ext extended addressing mode sp stack pointer ff offset byte in indexed, 8-bit offset addressing x index register h half-carry ?ag z zero ?ag hh ll high and low bytes of operand address in extended addressing # immediate value i interrupt mask logical and ii immediate operand byte logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode C( ) negation (twos complement) ix1 indexed, 8-bit offset addressing mode ? loaded with ix2 indexed, 16-bit offset addressing mode ? if m memory location : concatenated with n negative ?ag set or cleared n any bit not affected table 6. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles hinzc 21-hc05cpu cpu instruction set 54 cpu motorola table 7. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 ix inh inh imm dir ext ix2 ix1 ix 0123456789 abcdef 0 5 brset0 3 dir 5 bset0 2 dir 3 bra 2 rel 5 neg 2 dir 3 nega 1 inh 3 negx 1 inh 6 neg 2 ix1 5 neg 1ix 9 rti 1 inh 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 5 sub 3 ix2 4 sub 2 ix1 3 sub 1ix 0 1 5 brclr0 3 dir 5 bclr0 2 dir 3 brn 2 rel 6 rts 1 inh 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 5 cmp 3 ix2 4 cmp 2 ix1 3 cmp 1ix 1 2 5 brset1 3 dir 5 bset1 2 dir 3 bhi 2 rel 11 mul 1 inh 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 5 sbc 3 ix2 4 sbc 2 ix1 3 sbc 1ix 2 3 5 brclr1 3 dir 5 bclr1 2 dir 3 bls 2 rel 5 com 2 dir 3 coma 1 inh 3 comx 1 inh 6 com 2 ix1 5 com 1ix 10 swi 1 inh 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 5 cpx 3 ix2 4 cpx 2 ix1 3 cpx 1ix 3 4 5 brset2 3 dir 5 bset2 2 dir 3 bcc 2 rel 5 lsr 2 dir 3 lsra 1 inh 3 lsrx 1 inh 6 lsr 2 ix1 5 lsr 1ix 2 and 2 imm 3 and 2 dir 4 and 3 ext 5 and 3 ix2 4 and 2 ix1 3 and 1ix 4 5 5 brclr2 3 dir 5 bclr2 2 dir 3 bcs/blo 2 rel 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 5 bit 3 ix2 4 bit 2 ix1 3 bit 1ix 5 6 5 brset3 3 dir 5 bset3 2 dir 3 bne 2 rel 5 ror 2 dir 3 rora 1 inh 3 rorx 1 inh 6 ror 2 ix1 5 ror 1ix 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 5 lda 3 ix2 4 lda 2 ix1 3 lda 1ix 6 7 5 brclr3 3 dir 5 bclr3 2 dir 3 beq 2 rel 5 asr 2 dir 3 asra 1 inh 3 asrx 1 inh 6 asr 2 ix1 5 asr 1ix 2 ta x 1 inh 4 sta 2 dir 5 sta 3 ext 6 sta 3 ix2 5 sta 2 ix1 4 sta 1ix 7 8 5 brset4 3 dir 5 bset4 2 dir 3 bhcc 2 rel 5 asl/lsl 2 dir 3 asla/lsla 1 inh 3 aslx/lslx 1 inh 6 asl/lsl 2 ix1 5 asl/lsl 1ix 2 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 5 eor 3 ix2 4 eor 2 ix1 3 eor 1ix 8 9 5 brclr4 3 dir 5 bclr4 2 dir 3 bhcs 2 rel 5 rol 2 dir 3 rola 1 inh 3 rolx 1 inh 6 rol 2 ix1 5 rol 1ix 2 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 5 adc 3 ix2 4 adc 2 ix1 3 adc 1ix 9 a 5 brset5 3 dir 5 bset5 2 dir 3 bpl 2 rel 5 dec 2 dir 3 deca 1 inh 3 decx 1 inh 6 dec 2 ix1 5 dec 1ix 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 5 ora 3 ix2 4 ora 2 ix1 3 ora 1ix a b 5 brclr5 3 dir 5 bclr5 2 dir 3 bmi 2 rel 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 5 add 3 ix2 4 add 2 ix1 3 add 1ix b c 5 brset6 3 dir 5 bset6 2 dir 3 bmc 2 rel 5 inc 2 dir 3 inca 1 inh 3 incx 1 inh 6 inc 2 ix1 5 inc 1ix 2 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix c d 5 brclr6 3 dir 5 bclr6 2 dir 3 bms 2 rel 4 tst 2 dir 3 tsta 1 inh 3 tstx 1 inh 5 tst 2 ix1 4 tst 1ix 2 nop 1 inh 6 bsr 2 rel 5 jsr 2 dir 6 jsr 3 ext 7 jsr 3 ix2 6 jsr 2 ix1 5 jsr 1ix d e 5 brset7 3 dir 5 bset7 2 dir 3 bil 2 rel 2 stop 1 inh 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 5 ldx 3 ix2 4 ldx 2 ix1 3 ldx 1ix e f 5 brclr7 3 dir 5 bclr7 2 dir 3 bih 2 rel 5 clr 2 dir 3 clra 1 inh 3 clrx 1 inh 6 clr 2 ix1 5 clr 1ix 2 wait 1 inh 2 txa 1 inh 4 stx 2 dir 5 stx 3 ext 6 stx 3 ix2 5 stx 2 ix1 4 stx 1ix f inh = inherent rel = relative imm = immediate ix = indexed, no offset dir = direct ix1 = indexed, 8-bit offset ext = extended ix2 = indexed, 16-bit offset 0 msb of opcode in hexadecimal lsb of opcode in hexadecimal 0 5 brset0 3 dir number of cycles opcode mnemonic number of bytes/addressing mode lsb msb lsb msb lsb msb 22-hc05cpu motorola resets and interrupts 55 resets and interrupts contents resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 cop watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 low-voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 timer interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 input capture interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 output compare interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 timer overflow interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 1-mc68hc705p9 resets and interrupts resets 56 resets and interrupts motorola resets a reset immediately stops the operation of the instruction being executed, initializes certain control bits, and loads the program counter with a user-defined reset vector address. the following sources can generate resets: ? power-on reset (por) circuit ? reset pin ? cop watchdog figure 1. reset sources power-on reset a positive transition on the v dd pin generates a power-on reset. note: the power-on reset is strictly for power-up conditions and cannot be used to detect drops in power supply voltage. a 4064 t cyc (internal clock cycle) delay after the oscillator becomes active allows the clock generator to stabilize. if the reset pin is at logic zero at the end of 4064 t cyc , the mcu remains in the reset condition until the signal on the reset pin goes to logic one. dq ck s reset latch power-on reset cop watchdog (programmable option) internal clock rst to cpu and reset v dd subsystem s 2-mc68hc705p9 resets and interrupts resets motorola resets and interrupts 57 figure 2. power-on reset timing external reset a logic zero applied to the reset pin for one and one-half t cyc generates an external reset. a schmitt trigger senses the logic level at the reset pin. figure 3. external reset timing 1ffe 4064 t cyc v dd osc1 pin internal clock internal address bus notes: internal data bus 1ffe 1ffe 1ffe 1ffe 1ffe 1fff (note 1) 1. power-on reset threshold is typically between 1 v and 2 v. 2. internal clock, internal address bus, and internal data bus are not available externally. new pch new pcl table 1. external reset timing characteristic symbol min max unit reset pulse width t rl 1.5 t cyc internal clock internal address bus notes: internal data bus 1ffe 1ffe 1ffe 1ffe 1fff new pc 1. internal clock, internal address bus, and internal data bus are not available externally. 2. the next rising edge of the internal clock after the rising edge of reset initiates the reset sequence. new pch t rl new pc new pcl dummy op code reset 3-mc68hc705p9 resets and interrupts low-voltage protection 58 resets and interrupts motorola cop watchdog reset a timeout of the cop watchdog generates a cop reset. the cop watchdog is part of a software error detection system and must be cleared periodically to start a new timeout period. to clear the cop watchdog and prevent a cop reset, write a logic zero to bit 0 (copc) of the cop register at location $1ff0. low-voltage protection a drop in power supply voltage below the minimum operating v dd voltage is called a brownout condition. a brownout while the mcu is in a non-reset state can corrupt mcu operation and necessitate a power-on reset to resume operation. the best protection against brownout is an undervoltage sensing circuit that pulls the reset pin low when it detects a low-power supply voltage. the undervoltage sensing circuit may be made of discrete components or an integrated circuit can be used. for information about brownout and the cop watchdog, see the computer operating properly watchdog section. 4-mc68hc705p9 resets and interrupts interrupts motorola resets and interrupts 59 interrupts the following sources can generate interrupts: ? swi instruction ? irq/v pp pin ? capture/compare timer an interrupt temporarily stops normal program execution to process a particular event. an interrupt does not stop the operation of the instruction being executed, but takes effect when the current instruction completes its execution. interrupt processing automatically saves the cpu registers on the stack and loads the program counter with a user-defined interrupt vector address. software interrupt the software interrupt (swi) instruction causes a non-maskable interrupt. external interrupt an interrupt signal on the irq/v pp pin latches an external interrupt request. when the cpu completes its current instruction, it tests the irq latch. if the irq latch is set, the cpu then tests the i bit in the condition code register. if the i bit is clear, the cpu then begins the interrupt sequence. the cpu clears the irq latch during interrupt processing, so that another interrupt signal on the irq/v pp pin can latch another interrupt request during the interrupt service routine. as soon as the i bit is cleared during the return from interrupt, the cpu can recognize the new interrupt request. figure 4 shows the irq/v pp pin interrupt logic. 5-mc68hc705p9 resets and interrupts interrupts 60 resets and interrupts motorola figure 4. external interrupt logic setting the i bit in the condition code register disables external interrupts. interrupt triggering sensitivity of the irq/v pp pin is a programmable option. the irq/v pp pin can be negative-edge triggered or negative-edge- and low-level triggered. the level-sensitive triggering option allows multiple external interrupt sources to be wire-ored to the irq/v pp pin. an external interrupt request, shown in figure 5 , is latched as long as any source is holding the irq/v pp pin low. figure 5. external interrupt timing dq ck clr level-sensitive trigger (mor option) v dd external interrupt request reset vector fetch irq/v pp i (from ccr) irq (internal) t ilih t ilil t ilih irq/v pp pin irq 1 irq n . . . 6-mc68hc705p9 resets and interrupts interrupts motorola resets and interrupts 61 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h 2. the minimum t ilil should not be less than the number of interrupt service routine cycles plus 19 t cyc . 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h 2. the minimum t ilil should not be less than the number of interrupt service routine cycles plus 19 t cyc . timer interrupts the capture/compare timer can generate the following interrupts: ? input capture interrupt ? output compare interrupt ? timer overflow interrupt setting the i bit in the condition code register disables timer interrupts. input capture interrupt an input capture interrupt request occurs if the input capture flag, icf, becomes set while the input capture interrupt enable bit, icie, is also set. icf is in the timer status register, and icie is in the timer control register. output compare interrupt an output compare interrupt request occurs if the output compare flag, ocf, becomes set while the output compare interrupt enable bit, ocie, is also set. ocf is in the timer status register, and ocie is in the timer control register. table 2. external interrupt timing (v dd = 5.0 vdc) (1) characteristic symbol min max unit interrupt pulse width low (edge-triggered) t ilih 125 ns interrupt pulse period t ilil note (2) t cyc table 3. external interrupt timing (v dd = 3.3 vdc) (1) characteristic symbol min max unit interrupt pulse width low (edge-triggered) t ilih 250 ns interrupt pulse period t ilil note (2) t cyc 7-mc68hc705p9 resets and interrupts interrupts 62 resets and interrupts motorola timer overflow interrupt a timer overflow interrupt request occurs if the timer overflow flag, tof, becomes set while the timer overflow interrupt enable bit, toie, is also set. tof is in the timer status register, and toie is in the timer control register. interrupt processing the cpu takes the following actions to begin servicing an interrupt: ? stores the cpu registers on the stack in the order shown in figure 6 ? sets the i bit in the condition code register to prevent further interrupts ? loads the program counter with the contents of the appropriate interrupt vector locations: C $1ffc and $1ffd (software interrupt vector) C $1ffa and $1ffb (external interrupt vector) C $1ff8 and $1ff9 (timer interrupt vector) the return from interrupt (rti) instruction causes the cpu to recover the cpu registers from the stack as shown in figure 6 . 8-mc68hc705p9 resets and interrupts interrupts motorola resets and interrupts 63 figure 6. interrupt stacking order 1. the cop watchdog is programmable in the mask option register. table 4. reset/interrupt vector addresses function source local mask global mask priority (1 = highest) vector address reset power-on reset pin cop watchdog (1) none none none none 1 1 1 $1ffeC$1fff software interrupt (swi) user code none none same priority as instruction $1ffcC$1ffd external interrupt irq/v pp pin none i bit 2 $1ffaC$1ffb timer interrupts icf bit ocf bit tof bit icie bit ocie bit toie bit i bit 3 $1ff8C$1ff9 condition code register $00c0 (bottom of stack ) $00c1 $00c2 ? ? ? accumulator index register program counter (high byte) program counter (low byte) ? ? ? ? ? ? ? ? ? $00fd $00fe $00ff (top of stack) 1 2 3 4 5 5 4 3 2 1 unstacking order stacking order 9-mc68hc705p9 resets and interrupts interrupts 64 resets and interrupts motorola figure 7. interrupt flowchart external interrupt? i bit set? timer interrupt? fetch next instruction. swi instruction? rti instruction? stack pc, x, a, ccr. set i bit. load pc with interrupt vector. yes yes yes yes yes unstack ccr, a, x, pc. execute instruction. clear irq latch. no no no no no from reset 10-mc68hc705p9 motorola low-power modes 65 low-power modes contents stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 stop mode the stop instruction puts the mcu in its lowest power-consumption mode and has the following effects on the mcu: ? stops the internal oscillator, the cpu clock, and the internal clock, turning off the capture/compare timer, the cop watchdog, the siop, and the adc ? clears the i bit in the condition code register, enabling external interrupts ? clears the icie, ocie, and toie bits in the timer control register, disabling further timer interrupts the stop instruction does not affect any other registers or any i/o lines. the following events bring the mcu out of stop mode: ? an external interrupt signal on the irq/v pp pin a high-to-low transition on the irq/v pp pin loads the program counter with the contents of locations $1ffa and $1ffb. the timer resumes counting from the last value before the stop instruction. ? external reset a logic zero on the reset pin resets the mcu and loads the program counter with the contents of locations $1ffe and $1fff. the timer begins counting from $fffc. 1-mc68hc705p9 low-power modes stop mode 66 low-power modes motorola when the mcu exits stop mode, processing resumes after a stabilization delay of 4064 oscillator cycles. an active edge on the pd7/tcap pin during stop mode sets the icf flag when an external interrupt brings the mcu out of stop mode. an external interrupt also latches the value in the timer registers into the input capture registers. if a reset brings the mcu out of stop mode, then an active edge on the pd7/tcap pin during stop mode has no effect on the icf flag or the input capture registers. see figure 1 for stop recovery timing information. figure 1. stop recovery timing t ilih 4064 t cyc osc t rl reset irq/v pp irq/v pp internal clock internal address notes: 1. internal clocking from osc1 pin 2. edge-triggered external interrupt mask option 3. edge- and level-triggered external interrupt mask option 4. reset vector shown as example reset or interrupt vector fetch 1ffe 1ffe 1ffe 1ffe 1ffe 1fff (note 4) bus (note 3) (note 2) (note 1) 2-mc68hc705p9 low-power modes stop mode motorola low-power modes 67 figure 2 shows the sequence of events caused by the stop instruction. figure 2. stop instruction flowchart stop clear i bit in ccr reset? yes turn on oscillator external no (1) load pc with reset vector or (2) service interrupt a. save cpu registers on stack b. set i bit in ccr c. load pc with interrupt vector delay 4064 cycles to stabilize interrupt? clear timer interrupt flags and timer interrupt enable bits clear timer prescaler turn off oscillator yes no 3-mc68hc705p9 low-power modes wait mode 68 low-power modes motorola wait mode the wait instruction puts the mcu in an intermediate power-consumption mode and has the following effects on the mcu: ? clears the i bit in the condition code register, enabling interrupts ? stops the cpu clock, but allows the internal clock to drive the capture/compare timer, the cop watchdog, and the adc the wait instruction does not affect any other registers or any i/o lines. the following conditions restart the cpu clock and bring the mcu out of wait mode: ? external interrupt a high-to-low transition on the irq/v pp pin loads the program counter with the contents of locations $1ffa and $1ffb. ? timer interrupt input capture, output compare, and timer overflow interrupt requests load the program counter with the contents of locations $1ff8 and $1ff9. ? cop watchdog reset a timeout of the cop watchdog resets the mcu and loads the program counter with the contents of locations $1ffe and $1fff. software can enable timer interrupts so that the mcu can periodically exit wait mode to reset the cop watchdog. ? external reset a logic zero on the reset pin resets the mcu and loads the program counter with the contents of locations $1ffe and $1fff. 4-mc68hc705p9 low-power modes wait mode motorola low-power modes 69 figure 3 shows the sequence of events caused by the wait instruction. figure 3. wait instruction flowchart wait external interrupt? clear i bit in ccr stop cpu clock reset? no yes timer interrupt? yes yes restart cpu clock no no other on-chip interrupt sources? no (1) fetch reset vector or (2) service interrupt a. save cpu registers on stack b. set i bit in ccr c. vector to interrupt service routine 5-mc68hc705p9 low-power modes data-retention mode 70 low-power modes motorola figure 4 shows the effect of the stop and wait instructions on the cpu clock and the timer clock. figure 4. stop/wait clock logic data-retention mode in data-retention mode, the mcu retains ram contents and cpu register contents at v dd voltages as low as 2.0 vdc. the data-retention feature allows the mcu to remain in a low-power consumption state during which it retains data, but the cpu cannot execute instructions. to put the mcu in data-retention mode: 1. drive the reset pin to logic zero. 2. lower the v dd voltage. the reset pin must remain low continuously during data-retention mode. to take the mcu out of data-retention mode: 1. return v dd to normal operating voltage. 2. return the reset pin to logic one. cpu clock internal clock ? 2 ? 2 timer clock adc clock internal oscillator osc1 osc2 wait stop 6-mc68hc705p9 motorola parallel i/o ports 71 parallel i/o ports contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 port a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 port a data register (porta) . . . . . . . . . . . . . . . . . . . . . . . . . . .73 data direction register a (ddra) . . . . . . . . . . . . . . . . . . . . . . . . .74 port b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 port b data register (portb) . . . . . . . . . . . . . . . . . . . . . . . . . . .76 data direction register b (ddrb) . . . . . . . . . . . . . . . . . . . . . . . . .77 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 port c data register (portc) . . . . . . . . . . . . . . . . . . . . . . . . . . .79 data direction register c (ddrc) . . . . . . . . . . . . . . . . . . . . . . . . .80 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 port d data register (portd) . . . . . . . . . . . . . . . . . . . . . . . . . . .82 data direction register d (ddrd) . . . . . . . . . . . . . . . . . . . . . . . . .83 1-mc68hc705p9 parallel i/o ports introduction 72 parallel i/o ports motorola introduction twenty bidirectional pins and one input-only pin form four parallel input/output (i/o) ports. all the bidirectional port pins are programmable as inputs or outputs. note: connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. addr. name: r/w bit 7 654321 bit 0 $0000 port a data register (porta) read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset $0001 port b data register (portb) read: pb7 pb6 pb5 00000 write: reset: unaffected by reset $0002 port c data register (portc) read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: unaffected by reset $0003 port d data register (portd) read: pd7 0 pd5 10000 write: reset: unaffected by reset $0004 data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 00000000 $0005 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 00000 write: reset: 00000000 = unimplemented figure 1. parallel i/o port register summary 2-mc68hc705p9 parallel i/o ports port a motorola parallel i/o ports 73 port a port a is an 8-bit general-purpose i/o port. port a data register (porta) the port a data register contains a latch for each of the eight port a pins. pa[7:0] port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. $0006 data direction register c (ddrc) read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 00000000 $0007 data direction register d (ddrd) read: 0 0 ddrd5 00000 write: reset: 00000000 addr. name: r/w bit 7 654321 bit 0 = unimplemented figure 1. parallel i/o port register summary (continued) $0000 bit 7 654321 bit 0 read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset figure 2. port a data register (porta) 3-mc68hc705p9 parallel i/o ports port a 74 parallel i/o ports motorola data direction register a (ddra) data direction register a determines whether each port a pin is an input or an output. ddra[7:0] data direction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all eight port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pins by writing to the port a data register before changing data direction register a bits from 0 to 1. figure 4 shows the i/o logic of port a. figure 4. port a i/o circuit $0004 bit 7 654321 bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 00000000 figure 3. data direction register a (ddra) read data direction register a ($0004) write data direction register a ($0004) reset write port a data register ($0000) read port a data register ($0000) pax internal data bus pax ddrax 4-mc68hc705p9 parallel i/o ports port a motorola parallel i/o ports 75 writing a logic one to a ddra bit enables the output buffer for the corresponding port a pin; a logic zero disables the output buffer. when bit ddrax is a logic one, reading address $0000 reads the pax data latch. when bit ddrax is a logic zero, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 1 summarizes the operation of the port a pins. 1. hi-z = high impedance 2. writing affects data register, but does not affect input. table 1. port a pin operation data direction bit i/o pin mode accesses to data bit read write 0 input, hi-z (1) pin latch (2) 1 output latch latch 5-mc68hc705p9 parallel i/o ports port b 76 parallel i/o ports motorola port b port b is a 3-bit i/o port that shares its pins with the serial i/o port (siop). note: do not use port b for general-purpose i/o while the siop is enabled. port b data register (portb) the port b data register contains a latch for each of the three port b pins. pb[7:5] port b data bits these read/write bits are software programmable bits. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. note: writing to data direction register b does not affect the data direction of port b pins that are being used by the siop. however, data direction register b always determines whether reading port b returns the states of the latches or the states of the pins. sck serial clock when the siop is enabled, sck is the siop clock output (in master mode) or the siop clock input (in slave mode). $0001 bit 7 654321 bit 0 read: pb7 pb6 pb5 00000 write: reset: unaffected by reset alternate function: sck sdi sdo = unimplemented figure 5. port b data register (portb) 6-mc68hc705p9 parallel i/o ports port b motorola parallel i/o ports 77 sdi serial data input when the siop is enabled, sdi is the siop data input. sdo serial data output when the siop is enabled, sdo is the siop data output. data direction register b (ddrb) data direction register b determines whether each port b pin is an input or an output. note: enabling and then disabling the siop configures data direction register b for siop operation and can also change the port b data register. after disabling the siop, initialize data direction register b and the port b data register as your application requires. ddrb[7:5] data direction register b bits these read/write bits control port b data direction. reset clears ddrb[7:5], configuring all three port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pins by writing to the port b data register before changing data direction register b bits from 0 to 1. figure 7 shows the i/o logic of port b. $0005 bit 7 654321 bit 0 read: ddrb7 ddrb6 ddrb5 00000 write: reset: 00000000 = unimplemented figure 6. data direction register b (ddrb) 7-mc68hc705p9 parallel i/o ports port b 78 parallel i/o ports motorola figure 7. port b i/o logic writing a logic one to a ddrb bit enables the output buffer for the corresponding port b pin; a logic zero disables the output buffer. when bit ddrbx is a logic one, reading address $0001 reads the pbx data latch. when bit ddrbx is a logic zero, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 1 summarizes the operation of the port b pins. 1. hi-z = high impedance 2. writing affects data register, but does not affect input. table 2. port b pin operation data direction bit i/o pin mode accesses to data bit read write 0 input, hi-z (1) pin latch (2) 1 output latch latch read data direction register b ($0005) write data direction register b ($0005) reset write port b data register ($0001) read port b data register ($0001) pbx internal data bus pbx ddrbx 8-mc68hc705p9 parallel i/o ports port c motorola parallel i/o ports 79 port c port c is an 8-bit i/o port that shares five of its pins with the a/d converter (adc). the five shared pins are available for general-purpose i/o functions when the adc is disabled. port c data register (portc) the port c data register contains a latch for each of the eight port c pins. pc[7:0] port c data bits these read/write bits are software programmable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. v rh voltage reference high bit when the adc is turned on, the pc7/v rh pin is the positive adc reference voltage. an[3:0] analog input bits when the adc is turned on, the an0Can3 pins are software-selectable analog inputs. unused analog inputs can be used as digital inputs, but pins pc3/an3, pc4/an2, pc5/an1, and pc6/an0 cannot be used as digital outputs while the adc is on. only pins pc0, pc1, and pc2 can be used as digital outputs when the adc is on. $0002 bit 7 654321 bit 0 read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: unaffected by reset alternate function: v rh an0 an1 an2 an3 figure 8. port c data register (portc) 9-mc68hc705p9 parallel i/o ports port c 80 parallel i/o ports motorola the port c data register reads normally while the adc is on, except that the bit corresponding to the currently selected adc input pin reads as logic zero. writing to bits pc7Cpc3 while the adc is on can produce unpredictable adc results. data direction register c (ddrc) data direction register c determines whether each port c pin is an input or an output. ddrc[7:0] data direction register c bits these read/write bits control port c data direction. reset clears ddrc[7:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writing to the port c data register before changing data direction register c bits from 0 to 1. writing to bits ddrc7Cddrc3 while the adc is on can produce unpredictable adc results. figure 10 shows the i/o logic of port c. $0006 bit 7 654321 bit 0 read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 00000000 figure 9. data direction register c (ddrc) 10-mc68hc705p9 parallel i/o ports port c motorola parallel i/o ports 81 figure 10. port c i/o logic writing a logic one to a ddrc bit enables the output buffer for the corresponding port c pin; a logic zero disables the output buffer. when bit ddrcx is a logic one, reading address $0002 reads the pcx data latch. when bit ddrcx is a logic zero, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 1 summarizes the operation of the port c pins. 1. hi-z = high impedance 2. writing affects data register, but does not affect input. table 3. port c pin operation data direction bit i/o pin mode accesses to data bit read write 0 input, hi-z (1) pin latch (2) 1 output latch latch read data direction register c ($0006) write data direction register c ($0006) reset write port c data register ($0002) read port c data register ($0002) pcx internal data bus pcx ddrcx 11-mc68hc705p9 parallel i/o ports port d 82 parallel i/o ports motorola port d port d is a 2-bit port with one i/o pin and one input-only pin. port d shares the input-only pin, pd7/tcap, with the capture/compare timer. pd7/tcap is the timer input capture pin. the pd7/tcap pin can always be a general-purpose input, even if input capture interrupts are enabled. port d data register (portd) the port d data register contains a latch for each of the two port d pins. pd7 and pd5 port d data bits these read/write bits are software programmable. data direction of each port d pin is under the control of the corresponding bit in data direction register d. reset has no effect on port d data. tcap timer capture tcap is the input capture pin for the timer. $0003 bit 7 654321 bit 0 read: pd7 0 pd5 10000 write: reset: unaffected by reset alternate function: tcap = unimplemented figure 11. port d data register (portd) 12-mc68hc705p9 parallel i/o ports port d motorola parallel i/o ports 83 data direction register d (ddrd) data direction register d determines whether each port d pin is an input or an output. ddrd5 data direction register d bit this read/write bit controls the data direction of pin pd5. reset clears ddrd5, configuring pd5 as an input. 1 = pd5 configured as output 0 = pd5 configured as input note: avoid glitches on port d pins by writing to the port d data register before changing data direction register d bits from 0 to 1. figure 13 shows the i/o logic of port d. figure 13. port d i/o logic writing a logic one to a ddrd bit enables the output buffer for the corresponding port d pin; a logic zero disables the output buffer. $0007 bit 7 654321 bit 0 read: 0 0 ddrd5 00000 write: reset: 00000000 = unimplemented figure 12. data direction register d (ddrd) read data direction register d ($0007) write data direction register d ($0007) reset write port d data register ($0003) read port d data register ($0003) pdx internal data bus pdx ddrdx 13-mc68hc705p9 parallel i/o ports port d 84 parallel i/o ports motorola when bit ddrdx is a logic one, reading address $0003 reads the pdx data latch. when bit ddrdx is a logic zero, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 1 summarizes the operation of the port d pins. 1. hi-z = high impedance 2. writing affects data register, but does not affect input. table 4. port d pin operation data direction bit i/o pin mode accesses to data bit read write 0 input, hi-z (1) pin latch (2) 1 output latch latch 14-mc68hc705p9 motorola cop 85 computer operating properly watchdog cop contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 cop watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 cop watchdog timeout period . . . . . . . . . . . . . . . . . . . . . . . . . . .86 clearing the cop watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 cop register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 features ? protection from runaway software ? 65.5-ms timeout period (with 2-mhz bus frequency) ? wait mode operation 1-cop0cop cop introduction 86 cop motorola introduction the purpose of the computer operating properly (cop) watchdog is to reset the mcu in case of software failure. software that is operating properly periodically services the cop watchdog and prevents the reset from occurring. the cop watchdog function is programmable in the mask option register. operation cop watchdog timeout the cop watchdog is a 16-bit counter that generates a reset if allowed to time out. periodically clearing the counter starts a new timeout period and prevents the cop from resetting the mcu. a cop watchdog timeout indicates that the software is not executing instructions in the correct sequence. note: the internal clock drives the cop watchdog. therefore, the cop watchdog cannot generate a reset for errors that cause the internal clock to stop. the cop watchdog also depends on a power supply voltage at or above a minimum specification and is not guaranteed to protect against brownout. for information about brownout protection, see the resets and interrupts section. cop watchdog timeout period use the following formula to calculate the cop timeout period: where cop timeout period 131 072 cycles , f bus -------------------------------------- - = f bus crystal frequency 2 -------------------------------------------- - = 2-cop0cop cop interrupts motorola cop 87 clearing the cop watchdog to clear the cop watchdog and prevent a cop reset, write a logic zero to bit 0 (copc) of the cop register at location $1ff0. if the main program executes within the cop timeout period, the clearing routine needs to be executed only once. if the main program takes longer than the cop timeout period, the clearing routine must be executed more than once. note: place the clearing routine in the main program and not in an interrupt routine. clearing the cop watchdog in an interrupt routine might prevent cop watchdog timeouts even though the main program is not operating properly. interrupts the cop watchdog does not generate interrupts. cop register the cop register is a write-only register that returns the contents of eprom location $1ff0 when read. copc cop clear copc is a write-only bit. periodically writing a logic zero to copc prevents the cop watchdog from resetting the mcu. reset clears the copc bit. $1ff0 bit 7 654321 bit 0 read: d7 d6 d5 d4 d3 d2 d1 d0 write: copc reset: uuuuuuu0 = unimplemented u = unaffected figure 1. cop register (copr) 3-cop0cop cop low-power modes 88 cop motorola low-power modes the stop and wait instructions put the mcu in low-power consumption standby modes. stop mode the stop instruction clears the cop watchdog counter. upon exit from stop mode by external reset: ? the counter begins counting from $0000. ? the counter is cleared again after the 4064-cycle oscillator stabilization delay. upon exit from stop mode by external interrupt: ? the counter begins counting from $0000. ? the counter is not cleared again after the oscillator stabilization delay and has a count of 4064 when the program resumes. wait mode the cop watchdog continues to operate normally after a wait instruction. software should periodically take the mcu out of wait mode and write to the copc bit to prevent a cop watchdog timeout. 4-cop0cop motorola timer 89 timer contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 pd7/tcap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 tcmp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 timer control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 timer status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 alternate timer registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 input capture registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 output compare registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 1-tim1ic1oc_a timer features 90 timer motorola features ? programmable polarity of input capture edge ? programmable polarity of output compare signal ? alternate counter registers ? 16-bit counter ? interrupt-driven operation with three maskable interrupt flags: C input capture C output compare C timer overflow introduction the timer provides a timing reference for mcu operations. the input capture and output compare functions provide a means to latch the times at which external events occur, to measure input waveforms, and to generate output waveforms and timing delays. figure 1 shows the structure of the timer module. 2-tim1ic1oc_a timer introduction motorola timer 91 figure 1. timer block diagram tcap edge select/ 16-bit comparator ocrh ocrl 16-bit counter tcmp ? 4 detect logic pin control logic trh trl icrh icrl icie toie ocie iedg olvl icf ocf tof timer overflow internal clock (xtal ? 2) internal data bus timer interrupt request atrl atrh 3-tim1ic1oc_a timer introduction 92 timer motorola addr. name r/w bit 7 654321 bit 0 $0012 timer control register (tcr) read: icie ocie toie 0 0 0 iedg olvl write: reset: 000000u0 $0013 timer status register (tsr) read: icf ocf tof 00000 write: reset: u u u 00000 $0014 input capture register high (icrh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: unaffected by reset $0015 input capture register low (icrl) read: bit 7 654321 bit 0 write: reset: unaffected by reset $0016 output compare register high (ocrh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: unaffected by reset $0017 output compare register low (ocrl) read: bit 7 654321 bit 0 write: reset: unaffected by reset $0018 timer register high (trh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: reset initializes trh to $ff $0019 timer register low (trl) read: bit 7 654321 bit 0 write: reset: reset initializes trl to $fc $001a alternate timer register high (atrh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: reset initializes atrh to $ff $001b alternate timer register low (atrl) read: bit 7 654321 bit 0 write: reset: reset initializes atrl to $fc = unimplemented u = unaffected figure 2. timer i/o register summary 4-tim1ic1oc_a timer operation motorola timer 93 operation the timing reference for the input capture and output compare functions is a 16-bit free-running counter. the counter is preceded by a divide-by- four prescaler and rolls over every 2 18 cycles. timer resolution with a 4- mhz crystal is 2 m s. software can read the value in the counter at any time without affecting the counter sequence. because of the 16-bit timer architecture, the i/o registers for the input capture and output compare functions are pairs of 8-bit registers. pin functions the timer uses two pins. pd7/tcap pd7/tcap is the input capture pin. when an active edge occurs on pd7/tcap, the timer transfers the current counter value to the input capture registers. pd7/tcap is also an i/o port pin. tcmp tcmp is the output-only output compare pin. when the counter value matches the value written in the output compare registers, the timer transfers the output level bit, olvl, to the tcmp pin. input capture the input capture function is a means to record the time at which an external event occurs. when the input capture circuitry detects an active edge on the pd7/tcap pin, it latches the contents of the timer registers into the input capture registers. the polarity of the active edge is programmable. latching values into the input capture registers at successive edges of the same polarity measures the period of the input signal on the pd7/tcap pin. latching the counter values at successive edges of opposite polarity measures the pulse width of the signal. figure 3 shows the logic of the input capture function. 5-tim1ic1oc_a timer operation 94 timer motorola figure 3. input capture operation output compare the output compare function is a means of generating an output signal when the 16-bit counter reaches a selected value. software writes the selected value into the output compare registers. on every fourth internal clock cycle the output compare circuitry compares the value of the counter to the value written in the output compare registers. when a match occurs, the timer transfers the programmable output level bit (olvl) from the timer control register to the tcmp pin. software can use the output compare register to measure time periods, to generate timing delays, or to generate a pulse of specific duration or a pulse train of specific frequency and duty cycle on the tcmp pin. figure 4 shows the logic of the output compare function. figure 4. output compare operation tcap edge select/ detect logic trh trl icrh icrl icie iedg icf timer interrupt request 16-bit comparator ocrh ($0016) ocrl ($0017) 16-bit counter tcmp pin control logic ocie olvl ocf timer interrupt request 6-tim1ic1oc_a timer timing motorola timer 95 timing 1. v dd = 5.0 vdc 10%, t a = t l to t h unless otherwise noted. 2. a 2-bit prescaler in the timer is the limiting factor as it counts 4 t cyc . 3. the minimum t tltl should not be less than the number of interrupt service routine cycles plus 19 t cyc . 1. v dd = 3.3 vdc 10%, t a = t l to t h unless otherwise noted. 2. a 2-bit prescaler in the timer is the limiting factor as it counts 4 t cyc . 3. the minimum t tltl should not be less than the number of interrupt service routine cycles plus 19 t cyc . figure 5. input capture characteristics table 1. timer characteristics (v dd = 5.0 vdc) (1) characteristic symbol min max unit timer resolution (2) t resl 4.0 t cyc input capture pulse width t h , t l 125 ns input capture pulse period t tltl note (3) t cyc table 2. timer characteristics (v dd = 3.3 vdc) (1) characteristic symbol min max unit timer resolution (2) t resl 4.0 t cyc input capture pulse width t h , t l 250 ns input capture pulse period t tltl note (3) t cyc t tltl t th t tl 7-tim1ic1oc_a timer timing 96 timer motorola figure 6. timer reset timing figure 7. input capture timing internal internal timer t00 t01 t10 t11 ? ? ? ? ? ? ? ? ? ? ? ? r eset (external or end of por) 16-bit $fffe $ffff $fffd $fffc clocks reset bus clock counter internal timer t00 t01 t10 t11 ? ? ? ? ? ? ? ? ? ? ? ? input capture 16-bit $ffeb $ffed $ffee $ffec note: input capture previously captured value $ffed input capture input capture $ffef if the input capture edge occurs in the shaded area between t10 states, then the input capture ?ag becomes set during the next t11 state. bus clock clocks counter edge latch register flag 8-tim1ic1oc_a timer timing motorola timer 97 figure 8. output compare timing figure 9. timer overflow timing internal timer t00 t01 t10 t11 ? ? ? ? ? ? ? ? ? ? ? ? output compare 16-bit $ffeb $ffed $ffee $ffec output compare $ffed cpu writes $ffed $ffef flag and tcmp registers notes: 1. a write to the output compare registers may occur at any time, but a compare only occurs at timer state t01. therefore, the compare may follow the write by up to four cycles. 2. the output compare ?ag is set at the timer state t11 that follows the comparison latch. bus clock clocks counter compare register latch $ffff $0001 $0002 $0000 internal timer t00 t01 t10 t11 ? ? ? ? ? ? ? ? ? ? ? ? overflow 16-bit flag (tof) bus clock clocks counter 9-tim1ic1oc_a timer interrupts 98 timer motorola interrupts the following timer sources can generate interrupts: ? input capture flag (icf) the icf bit is set when an edge of the selected polarity occurs on the input capture pin. the input capture interrupt enable bit, icie, enables icf interrupt requests. ? output compare flag (ocf) the ocf bit is set when the counter value matches the value written in the output compare registers. the output compare interrupt enable bit, ocie, enables ocf interrupt requests. ? timer overflow flag (tof) the tof bit is set when the counter value rolls over from $ffff to $0000. the timer overflow enable bit (toie) enables timer overflow interrupt requests. table 3 summarizes the timer interrupt sources. i/o registers the following registers control and monitor the operation of the timer: ? timer control register (tcr) ? timer status register (tsr) ? timer registers (trh and trl) ? alternate timer registers (atrh and atrl) ? input capture registers (icrh and icrl) ? output compare registers (ocrh and ocrl) table 3. timer interrupt sources source local mask global mask priority (1 = highest) icf bit ocf bit tof bit icie bit ocie bit toie bit i bit 3 10-tim1ic1oc_a timer i/o registers motorola timer 99 timer control register the timer control register (tcr) performs the following functions: ? enables input capture interrupts ? enables output compare interrupts ? enables timer overflow interrupts ? controls the active edge polarity of the tcap signal ? controls the active level of the tcmp output icie input capture interrupt enable this read/write bit enables interrupts caused by an active signal on the pd7/tcap pin. reset clears the icie bit. 1 = input capture interrupts enabled 0 = input capture interrupts disabled ocie output compare interrupt enable this read/write bit enables interrupts caused by an active signal on the tcmp pin. reset clears the ocie bit. 1 = output compare interrupts enabled 0 = output compare interrupts disabled toie timer overflow interrupt enable this read/write bit enables interrupts caused by a timer overflow. reset clears the toie bit. 1 = timer overflow interrupts enabled 0 = timer overflow interrupts disabled bits 4C2 unused these are read/write bits that always read as logic zeros. $0012 bit 7 654321 bit 0 read: icie ocie toie 0 0 0 iedg olvl write: reset: 000000u0 u = unaffected figure 10. timer control register (tcr) 11-tim1ic1oc_a timer i/o registers 100 timer motorola iedg input edge the state of this read/write bit determines whether a positive or negative transition on the pd7/tcap pin triggers a transfer of the contents of the timer registers to the input capture registers. reset has no effect on the iedg bit. 1 = positive edge (low-to-high transition) triggers input capture 0 = negative edge (high-to-low transition) triggers input capture olvl output level the state of this read/write bit determines whether a logic one or a logic zero appears on the tcmp pin when a successful output compare occurs. reset clears the olvl bit. 1 = tcmp goes high on output compare 0 = tcmp goes low on output compare timer status register the timer status register (tsr) contains flags for the following events: ? an active signal on the pd7/tcap pin, transferring the contents of the timer registers to the input capture registers ? a match between the 16-bit counter and the output compare registers, transferring the olvl bit to the tcmp pin ? a timer rollover from $ffff to $0000 $0013 bit 7 654321 bit 0 read: icfocftof00000 write: reset: u u u 00000 = unimplemented u = unaffected figure 11. timer status register (tsr) 12-tim1ic1oc_a timer i/o registers motorola timer 101 icf input capture flag the icf bit is automatically set when an edge of the selected polarity occurs on the pd7/tcap pin. clear the icf bit by reading the timer status register with icf set, and then reading the low byte of the input capture registers. reset has no effect on icf. 1 = input capture 0 = no input capture ocf output compare flag the ocf bit is automatically set when the value of the timer registers matches the contents of the output compare registers. clear the ocf bit by reading the timer status register with ocf set, and then reading the low byte of the output compare registers. reset has no effect on ocf. 1 = output compare 0 = no output compare tof timer overflow flag the tof bit is automatically set when the 16-bit counter rolls over from $ffff to $0000. clear the tof bit by reading the timer status register with tof set, and then reading the low byte of the timer registers. reset has no effect on tof. 1 = timer overflow 0 = no timer overflow 13-tim1ic1oc_a timer i/o registers 102 timer motorola timer registers the read-only timer registers (trh and trl) contain the current high and low bytes of the 16-bit counter. reading trh before reading trl causes trl to be latched until trl is read. reading trl after reading the timer status register clears the timer overflow flag (tof). writing to the timer registers has no effect. reading trh returns the current value of the high byte of the counter and causes the low byte to be latched into a buffer. the buffer value remains fixed even if the high byte is read more than once. reading trl reads the transparent low byte buffer and completes the read sequence of the timer registers. figure 13. timer register reads note: to prevent interrupts from occurring between readings of trh and trl, set the interrupt mask (i bit) in the condition code register before reading trh, and clear the mask after reading trl. $0018 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: reset initializes trh to $ff $0019 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: reset initializes trl to $fc = unimplemented figure 12. timer registers (trh and trl) trh ($0018) trl ($0019) buffer internal data bus read trh latch 14-tim1ic1oc_a timer i/o registers motorola timer 103 alternate timer registers the read-only alternate timer registers (atrh and atrl) contain the current high and low bytes of the 16-bit counter. reading atrh before reading atrl causes atrl to be latched until atrl is read. reading does not affect the timer overflow flag (tof). writing to the alternate timer registers has no effect. reading atrh returns the current value of the high byte of the counter and causes the low byte to be latched into a buffer. figure 15. alternate timer register reads note: to prevent interrupts between readings of atrh and atrl, set the interrupt mask (i bit) in the condition code register before reading atrh, and clear the mask after reading atrl. $001a bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: reset initializes atrh to $ff $001b bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: reset initializes atrl to $fc = unimplemented figure 14. alternate timer registers (atrh and atrl) atrh ($001a) atrl ($001b) buffer internal data bus read atrh latch 15-tim1ic1oc_a timer i/o registers 104 timer motorola input capture registers when a selected edge occurs on the tcap pin, the current high and low bytes of the 16-bit counter are latched into the read-only input capture registers (icrh and icrl). reading icrh before reading icrl inhibits further captures until icrl is read. reading icrl after reading the timer status register clears the input capture flag (icf). writing to the input capture registers has no effect. note: to prevent interrupts between readings of icrh and icrl, set the interrupt mask (i bit) in the condition code register before reading icrh, and clear the mask after reading icrl. $0014 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: unaffected by reset $0015 76543210 read: bit 7 6 5 4 3 2 1 bit 0 write: reset: unaffected by reset = unimplemented figure 16. input capture registers (icrh and icrl) 16-tim1ic1oc_a timer i/o registers motorola timer 105 output compare registers when the value of the 16-bit counter matches the value in the read/write output compare registers (ocrh and ocrl), the planned tcmp pin action takes place. writing to ocrh before writing to ocrl inhibits timer compares until ocrl is written. reading or writing to ocrl after reading the timer status register clears the output compare flag (ocf). to prevent ocf from being set between the time it is read and the time the output compare registers are updated, use the following procedure: 1. disable interrupts by setting the i bit in the condition code register. 2. write to ocrh. compares are now inhibited until ocrl is written. 3. clear bit ocf by reading the timer status register (tsr). 4. enable the output compare function by writing to ocrl. 5. enable interrupts by clearing the i bit in the condition code register. $0016 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: unaffected by reset $0017 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: unaffected by reset figure 17. output compare registers (ocrh and ocrl) 17-tim1ic1oc_a timer low-power modes 106 timer motorola low-power modes the stop and wait instructions put the mcu in low-power consumption standby modes. stop mode the stop instruction suspends the timer counter. upon exit from stop mode by external reset: ? the timer counter resumes counting from $fffc. ? an input capture edge during stop mode does not affect the icf bit or the input capture registers. upon exit from stop mode by external interrupt: ? the counter resumes counting from the suspended value. ? an input capture edge during stop mode sets the icf bit and transfers the suspended timer counter value to the input capture registers. wait mode the timer remains active after a wait instruction. any enabled timer interrupt request can bring the mcu out of wait mode. 18-tim1ic1oc_a motorola siop 107 serial input/output port siop contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 pb7/sck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 pb5/sdo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 pb6/sdi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 data movement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 siop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 siop status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 siop data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120 1-siop_a siop features 108 siop motorola features ? master or slave operation ? programmable msb-first or lsb-first operation ? interrupt-driven operation with transfer complete flag ? data collision flag ? master mode frequency = bus frequency ? 4 ? maximum slave mode frequency = bus frequency ? ? 4 ? no minimum slave mode frequency introduction the serial input/output port (siop) is a 3-wire master/slave communication port with serial clock, data input, and data output connections. the siop enables high-speed synchronous serial data transfer between the mcu and peripheral devices. shift registers used with the siop can increase the number of parallel i/o pins controlled by the mcu. more powerful peripherals such as analog-to-digital converters and real-time clocks are also compatible with the siop. figure 1 shows the structure of the siop module. 2-siop_a siop introduction motorola siop 109 figure 1. siop block diagram addr. name bit 7 654321 bit 0 $000a siop control register (scr) read: 0 spe 0 mstr 0000 write: reset: 00000000 $000b siop status register (ssr) read: spif dcol 000000 write: reset: 00000000 $000c siop data register (sdr) read: bit 7 654321 bit 0 write: reset: unaffected by reset = unimplemented figure 2. siop i/o register summary spe spif dcol mstr siop 76543210 siop data register clock logic divide by 4 pin control logic and ddr siop control internal clock (f osc ? 2) internal bus from mor shift clock spif/dcol ms pb5/sdo pb7/sck pb6/sdi 3-siop_a siop operation 110 siop motorola operation the master mcu initiates and controls the transfer of data to and from one or more slave peripheral ?devices. in master mode, a transmission is initiated by writing to the siop data register (sdr). data written to the sdr is parallel-loaded and shifted out serially to the slave device(s). many simple slave devices are designed to only receive data from a master or to only supply data to a master. for example, when a serial-to-parallel shift register is used as an 8-bit port, the master mcu initiates transfers of 8-bit data values to the shift register. since the serial-to-parallel shift register does not send any data to the master, the mcu ignores whatever it receives as a result of the transmission. the siop is simpler than the serial peripheral interface (spi) on some other motorola mcus in that: ? the polarity of the serial clock is fixed. ? there is no slave select pin. ? the direction of serial data does not automatically switch as on the spi because the siop is not intended for use in multimaster systems. most applications use one mcu as the master to initiate and control data transfer between one or more slave peripheral devices. a programmable option allows the siop to transfer data msb first or lsb first. 4-siop_a siop operation motorola siop 111 pin functions the siop uses three pins and shares them with port b: ? pb7/sck ? pb6/sdi ? pb5/sdo note: do not use the pb7/sck, pb6/sdi, or pb5/sdo pins for general-purpose i/o while the siop is enabled. when bit 6 (spe) of the siop control register (scr) is set, the siop is enabled and the pb7/sck, pb5/sdo, and pb6/sdi pins are dedicated to siop functions. clearing spe disables the siop and the siop pins become standard i/o port pins. note: enabling and then disabling the siop configures the data direction register bits associated with the siop pins for siop operation and can also change the associated port data register. after disabling the siop, initialize the data direction register and the port data register as the application requires. pb7/sck the pb7/sck pin synchronizes the movement of data into and out of the mcu through the pb6/sdi and pb5/sdo pins. in master mode, the pb7/sck pin is an output. the serial clock frequency in master mode is one-fourth the internal clock frequency. in slave mode, the pb7/sck pin is an input. the maximum serial clock frequency in slave mode is one-fourth the internal clock rate. slave mode has no minimum serial clock frequency. 5-siop_a siop operation 112 siop motorola figure 3 shows the timing relationships among the serial clock, data input, and data output. the state of the serial clock between transmissions is a logic one. the first falling edge on the pb7/sck pin signals the beginning of a transmission, and data appears at the pb5/sdo pin. data is captured at the pb6/sdi pin on the rising edge of the serial clock, and the transmission ends on the eighth rising edge of the serial clock. figure 3. siop data/clock timing the first falling edge on pb7/sck begins a transmission. at this time the first bit of received data is accepted at the pb6/sdi pin and the first bit of transmitted data is presented at the pb5/sdo pin. pb5/sdo the pb5/sdo pin is the siop data output. between transfers, the state of the pb5/sdo pin reflects the value of the last bit shifted out on the previous transmission, if there was one. to preset the beginning state, write to the corresponding port data bit before enabling the siop. on the first falling edge on the pb7/sck pin, the first data bit to be shifted out appears at the pb5/sdo pin. after spe is set, the pb5/sdo output driver can be disabled by writing a zero to the corresponding data direction register bit of the port, thereby configuring pb5/sdo as a high-impedance input. msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb serial clock data output data output sample input lsb bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 msb (msb-first option) (lsb-first option) 6-siop_a siop operation motorola siop 113 pb6/sdi the pb6/sdi pin is the siop data input. valid sdi data must be present for an sdi setup time, t s , before the rising edge of the serial clock and must remain valid for an sdi hold time, t h , after the rising edge of the serial clock. (see table 1 and table 2 .) data movement connecting the siop data register of a master mcu with the siop of a slave mcu forms a 16-bit circular shift register. during an siop transfer, the master shifts out the contents of its siop data register on its pb5/sdo pin. at the same time, the slave mcu shifts out the contents of its siop data register on its pb5/sdo pin. figure 4 shows how the master and slave exchange the contents of their data registers. figure 4. master/slave siop shift register operation siop shift register sdo sdi siop shift register sdi sdo sck sck siop in slave mode siop in master mode 7-siop_a siop timing 114 siop motorola timing figure 5. siop timing 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h unless otherwise noted. 2. t cyc = 1 ? f op 3. f osc = crystal frequency; f op = f osc ? 2 = 2.1 mhz maximum 4. in master mode, the frequency of sck is f op ? 4. table 1. siop timing (v dd = 5.0 vdc) (1) characteristic symbol min max unit frequency of operation master slave f siop ( m ) f siop ( s ) f osc /64 dc f osc /8 525 mhz khz cycle time master slave t sck ( m ) t sck ( s ) 4.0 4.0 1920 t cyc (2) ns clock (sck) low time (f op = 2.1 mhz) (3)(4) t sckl 932 ns sdo data valid time t v 200 ns sdo hold time t ho 0ns sdi setup time t s 100 ns sdi hold time t h 100 ns msb t sck t sckl bit 1 t v msb valid data lsb lsb t s t ho t h sck sdo sdi 8-siop_a siop interrupts motorola siop 115 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h unless otherwise noted 2. t cyc = 1 ? f op 3. f osc = crystal frequency; f op = f osc ? 2 = 1.0 mhz maximum 4. in master mode, the frequency of sck is f op ? 4. interrupts the siop does not generate interrupt requests. table 2. siop timing (v dd = 3.3 vdc) (1) characteristic symbol min max unit frequency of operation master slave f siop ( m ) f siop ( s ) f osc /64 dc f osc /8 250 mhz khz cycle time master slave t sck ( m ) t sck ( s ) 4.0 4.0 4000 t cyc (2) clock (sck) low time (f op = 1.0 mhz) (3) (4) t sckl 1980 ns sdo data valid time t v 400 ns sdo hold time t ho 0ns sdi setup time t s 200 ns sdi hold time t h 200 ns 9-siop_a siop i/o registers 116 siop motorola i/o registers the following registers control and monitor siop operation: ? siop control register (scr) ? siop status register (ssr) ? siop data register (sdr) siop control register the read/write siop control register (scr) contains two bits. one bit enables the siop, and the other configures the siop for master mode or for slave mode. spe siop enable this read/write bit enables the siop. setting spe initializes the data direction register as follows: ? the pb6/sdi pin is an input. ? the pb5/sdo pin is an output. ? the pb7/sck pin is an input in slave mode and an output in master mode. clearing spe disables the siop and returns the port to its normal i/o functions. the data direction register and the port data register remain in their siop-initialized state. note: after clearing spe, be sure to initialize the port for its intended i/o use. $000a bit 7 654321 bit 0 read: 0 spe 0 mstr 0000 write: reset: 00000000 figure 6. siop control register (scr) 10-siop_a siop i/o registers motorola siop 117 clearing spe during a transmission aborts the transmission, resets the bit counter, and returns the port to its normal i/o function. reset clears spe. 1 = siop enabled 0 = siop disabled mstr master mode select this read/write bit configures the siop for master mode. setting mstr initializes the pb7/sck pin as the serial clock output. clearing mstr initializes the pb7/sck pin as the serial clock input. mstr can be set at any time regardless of the state of spe. reset clears mstr. 1 = master mode selected 0 = slave mode selected 11-siop_a siop i/o registers 118 siop motorola siop status register the read-only siop status register (ssr) contains two bits. one bit indicates that a siop transfer is complete, and the other indicates that an invalid access of the siop data register occurred while a transfer was in progress. spif serial peripheral interface flag this clearable, read-only bit is set automatically on the eighth rising edge on the pb7/sck pin and indicates that a data transmission took place. spif does not inhibit further transmissions. clear spif by reading the siop status register while spif is set and then reading or writing the siop data register. reset clears spif. 1 = transmission complete 0 = transmission not complete $000b bit 7 654321 bit 0 read: spif dcol 000000 write: reset: 00000000 figure 7. siop status register (ssr) 12-siop_a siop i/o registers motorola siop 119 dcol data collision flag this clearable, read-only bit is automatically set if the siop data register is accessed while a data transfer is in progress. reading or writing the siop data register while a transmission is in progress causes invalid data to be transmitted or read. clear dcol by reading the siop status register with spif set and then accessing the siop data register. because the clearing sequence accesses the siop data register, the sequence has to be completed before another transmission starts or dcol is set again. to clear dcol when spif is not set, turn off the siop by writing a zero to spe and then turn it back on by writing a one to spe. reset clears dcol. 1 = invalid access of sdr 0 = valid access of sdr siop data register the siop data register (sdr) is both the transmit data register and the receive data register. to read or write the siop data register, the spe bit in the siop control register must be set. with the siop configured for master mode, writing to the siop data register initiates a serial transfer. this register is not buffered. writing to the siop data register overwrites the previous contents. reading or writing to the siop data register while a transmission is in progress can cause invalid data to be transmitted or received. $000c bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: unaffected by reset figure 8. siop data register (sdr) 13-siop_a siop low-power modes 120 siop motorola low-power modes the wait and stop instructions put the mcu in low-power consumption standby modes. stop mode the stop instruction suspends the clock to the siop. when the mcu exits stop mode, processing resumes after the internal oscillator stabilization delay of 4064 oscillator cycles. a stop instruction in a master siop does not suspend the clock to slave siops. wait mode the wait instruction suspends the clock to the siop. when the mcu exits wait mode, processing resumes immediately. a wait instruction in a master siop does not suspend the clock to slave siops. 14-siop_a motorola adc 121 analog-to-digital converter adc contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 pc7/v rh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 pc6/an0Cpc3/an3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 timing and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . .125 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126 adc status and control register . . . . . . . . . . . . . . . . . . . . . . . .126 adc data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 features ? 8-bit conversions with 1.5-lsb precision ? four external and three internal analog input channels ? wait mode operation 1-atd4x8nvrl adc introduction 122 adc motorola introduction the adc consists of a single successive-approximation a/d converter, an input multiplexer to select one of four external or two internal channels, and control circuitry. figure 1 shows the structure of the adc module. figure 1. adc block diagram ch2 ch1 ch0 input multiplexer digital- to-analog converter adon ccf internal rc oscillator adrc an3 an2 an1 an1 v rh v ss internal clock (xtal ? 2) comparator internal data bus control logic 2-atd4x8nvrl adc operation motorola adc 123 operation the a/d conversion process is ratiometric, using two reference voltages, v rh and v ss . conversion accuracy is guaranteed only if v rh is equal to v dd . pin functions the adc uses five pins and shares them with port c: ? pc7/v rh ? pc6/an0, pc5/an1, pc4/an2, and pc3/an3 pc7/v rh the voltage reference high pin (pc7/v rh ) supplies the high reference voltage for the ratiometric conversion process. for ratiometric conversion, the supply voltage of the analog source should be the same as v rh and be referenced to v ss . table 1. adc i/o register summary addr. name r/w bit 7 654321 bit 0 $001d adc data register (addr) read: bit 7 654321 bit 0 write: reset: unaffected by reset $001e adc status/control register (adscr) read: ccf adrc adon 00 ch2 ch1 ch0 write: reset: 00000000 = unimplemented 3-atd4x8nvrl adc interrupts 124 adc motorola pc6/an0C pc3/an3 the multiplexer can select one of four external analog input channels (an0, an1, an2, or an3) for sampling. the conversion takes 32 cycles. the first 12 cycles sample the voltage on the selected input pin by charging an internal capacitor. in the last 20 cycles, a comparator successively compares the output of an internal d/a converter to the sampled analog input. control logic changes the d/a converter input one bit at a time, starting with the msb, until the d/a converter output matches the sampled analog input. the conversion is monotonic and has no missing codes. at the end of the conversion, the conversion complete flag (ccf) becomes set, and the cpu takes two cycles to move the result to the adc data register. note: to prevent excess power dissipation, do not simultaneously use an i/o port pin as a digital input and an analog input. while the adc is on, the selected analog input reads as logic zero. the port c pins that are not selected read normally. an analog input voltage equal to v rh converts to digital $ff; an input voltage greater than v rh converts to $ff with no overflow. an analog input voltage equal to v ss converts to digital $00. for ratiometric conversion, the source of each analog input should use v rh as the supply voltage and be referenced to v ss . the clock frequency must be equal to or greater than 1 mhz. if the internal clock frequency is less than 1mhz, the internal rc oscillator (nominally 1.5 mhz) must be used for the adc conversion clock. make this selection by setting the adrc bit to logic one in the adc status and control register. interrupts the adc cannot generate interrupt requests. 4-atd4x8nvrl adc timing and electrical characteristics motorola adc 125 timing and electrical characteristics 1. v dd = 5.0 vdc 10%, v ss = 0 vdc 2. adc accuracy may decrease proportionately as v rh is reduced below 4.0 v. 3. t ad = cycle time of the a/d converter 4. source impedances more than 10 k w adversely affect internal rc charging time during input sampling. 5. t ad = t cyc (1 ? f op ) if mcu clock is clock source 6. external system error caused by input leakage approximately equals r source times input current. table 2. adc characteristics (v dd = 5.0 vdc) (1) characteristic min max unit resolution 8 8 bit absolute accuracy (4.0 > v rh > v dd ) (2) 1.5 lsb conversion range (pc7/v rh )v ss v dd v conversion time (includes sampling time) external clock internal rc oscillator (adrc = 1) 32 32 32 32 t ad (3) m s monotonicity inherent (within total error) zero input reading (v in = 0 v) 00 01 hex full-scale reading (v in = v rh )ffffhex sample acquisition time (4) external clock internal rc oscillator (adrc = 1) 12 12 12 t ad (5) m s input capacitance pc6/an0, pc5/an1, pc4/an2, pc3/an3 12pf analog input voltage v ss v rh v input leakage (6) pc6/an0, pc5/an1, pc4/an2, pc3/an3 pc7/v rh 1 1 m a adc on current stabilization time 100 m s 5-atd4x8nvrl adc i/o registers 126 adc motorola i/o registers the following registers control and monitor operation of the adc: ? adc status and control register (adscr) ? adc data register (addr) adc status and control register the adc status and control register (adscr) contains a conversion complete flag and four writable control bits. writing to adscr clears the conversion complete flag and starts a new conversion sequence. ccf conversion complete flag this read-only bit is automatically set when an analog-to-digital conversion is complete, and a new result can be read from the adc data register. clear the ccf bit by writing to the adc status and control register or by reading the adc data register. resets clear the ccf bit. 1 = conversion complete 0 = conversion not complete $001e bit 7 654321 bit 0 read: ccf adrc adon 00 ch2 ch1 ch0 write: reset: 00000000 = unimplemented figure 2. adc status and control register (adscr) 6-atd4x8nvrl adc i/o registers motorola adc 127 adrc adc rc (oscillator) this read/write bit turns on the internal rc oscillator to drive the adc. if the internal clock frequency (f op ) is less than 1 mhz, adrc must be set. when the rc oscillator is turned on, it requires a time, t adrc , to stabilize, and results can be inaccurate during this time. resets clear the adrc bit. 1 = internal rc oscillator drives adc 0 = internal clock drives adc when the internal rc oscillator is being used as the adc clock, two limitations apply: ? because of the frequency tolerance of the rc oscillator and its asynchronism with the internal clock, the conversion complete flag must be used to determine when a conversion sequence is complete. ? the conversion process runs at the nominal 1.5-mhz rate, but the conversion results must be transferred to the adc data register synchronously with the internal clock; therefore, the conversion process is limited to a maximum of one channel every internal clock cycle. adon adc on this read/write bit turns on the adc. when the adc is on, it requires a time, t adon , for the current sources to stabilize. during this time, results can be inaccurate. resets clear the adon bit. 1 = adc turned on 0 = adc turned off bits 4C2 not used bits 4C2 always read as logic zeros. 7-atd4x8nvrl adc i/o registers 128 adc motorola ch[2:0] channel select bits these read/write bits select one of eight adc input channels as shown in table 3 . channels 0C3 are the input pins, pc3/an3, pc4/an2, pc5/an1, and pc6/an0. channels 4C6 can be used for reference measurements. channel 7 is reserved for factory testing. to prevent excess power dissipation, do not use an adc pin as an analog input and a digital input at the same time. using one of the port pins as the adc input does not affect the ability to use the remaining port pins as digital inputs. reading a port pin that is selected as an analog input returns a logic zero. table 3. adc input channel selection ch[2:1:0] channel signal 000 0 an0 001 1 an1 010 2 an2 011 3 an3 100 4 v rh 101 5 (v rh + v ss ) / 2 110 6 v ss 111 7 reserved 8-atd4x8nvrl adc i/o registers motorola adc 129 adc data register the adc data register (addr) is a read-only register that contains the result of the most recent analog-to-digital conversion. $001d bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: unaffected by reset figure 3. adc data register (addr) 9-atd4x8nvrl adc low-power modes 130 adc motorola low-power modes stop mode the stop instruction turns off the adc and aborts any current and pending conversions. wait mode the adc continues to operate normally after the wait instruction. to reduce power consumption in wait mode: ? if the adc is not being used, clear both the adon and adrc bits before entering wait mode. ? if the adc is being used and the internal clock rate is above 1 mhz, clear the adrc bit before entering wait mode. 10-atd4x8nvrl motorola specifications 131 specifications contents maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 power considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 5.0 v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .135 3.3 v dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .136 driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 typical supply current vs. internal clock frequency . . . . . . . . . . . .138 maximum supply current vs. internal clock frequency . . . . . . . . . .139 5.0 v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140 3.3 v control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 test load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 28-pin pdip case #710 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 28-pin cerdip case #733 . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 28-pin soic case #751f . . . . . . . . . . . . . . . . . . . . . . . . . . . .144 1-mc68hc705p9 speci?cations maximum ratings 132 specifications motorola maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in table 1 . keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . note: this device is not guaranteed to operate properly at the maximum ratings. refer to 5.0 v dc electrical characteristics on page 135 and 3.3 v dc electrical characteristics on page 136 for guaranteed operating conditions. table 1. maximum ratings rating symbol value unit supply voltage v dd C0.3 to +7.0 v current drain per pin (excluding v dd and v ss ) i25ma input voltage v in v ss C 0.3 to v dd + 0.3 v eprom programming voltage v pp 16.75 v storage temperature range t stg C65 to +150 c 2-mc68hc705p9 specifications operating temperature range motorola specifications 133 operating temperature range thermal characteristics 1. p = plastic dual in-line package (pdip) 2. dw = small outline integrated circuit (soic) 3. s = ceramic dual in-line package (cerdip) 4. c = extended temperature range (C40 to +85 c) 5. v = automotive temperature range (C40 to +105 c) 6. m = automotive temperature range (C40 to +125 c) table 2. operating temperature range package type symbol value unit mc68hc705p9p (1) , dw (2) , s (3) (standard) mc68hc705p9c (4) p, cdw, cs (extended) mc68hc705p9v (5) p, vdw, vs (automotive) mc68hc705p9m (6) p, mdw, ms (automotive) t a t l to t h 0 to 70 C40 to +85 C40 to +105 C40 to +125 c table 3. thermal characteristics characteristic symbol value unit thermal resistance plastic dual in-line package (pdip) small outline integrated circuit (soic) ceramic dual in-line package (cerdip) q ja 60 60 60 c/w 3-mc68hc705p9 speci?cations power considerations 134 specifications motorola power considerations the average chip junction temperature, t j , in c can be obtained from: (1) where: t a = ambient temperature in c q ja = package thermal resistance, junction to ambient in c/w p d = p int + p i / o p int = i cc v cc = chip internal power dissipation p i / o = power dissipation on input and output pins (user-determined) for most applications, p i / o p int and can be neglected. ignoring p i / o , the relationship between p d and t j is approximately: (2) solving equations (1) and (2) for k gives: (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . t j t a p d q ja () + = p d k t j 273 c + --------------------------------- - = kp d t a 273 c + ()q ja p d () 2 + = 4-mc68hc705p9 specifications 5.0 v dc electrical characteristics motorola specifications 135 5.0 v dc electrical characteristics 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h unless otherwise noted 2. typical values at midpoint of voltage range, 25 c only 3. run mode and wait mode i dd measured using external square wave clock source (f osc = 4.2 mhz); all inputs 0.2 v from rail; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 4. wait mode and stop mode i dd measured with all ports configured as inputs; v il = 0.2 v; v ih = v dd C 0.2 v 5. stop mode i dd measured with osc1 = v ss 6. wait mode i dd affected linearly by osc2 capacitance table 4. dc electrical characteristics (v dd = 5.0 vdc) (1) characteristic symbol min typ (2) max unit output voltage i load = 10.0 m a i load = C10.0 m a v ol v oh v dd C 0.1 0.1 v output high voltage (i load = C0.8 ma) pa7Cpa0, pb7/sckCpb5/sdo, pc7/v rh Cpc0, pd5, tcmp v oh v dd C 0.8 v output low voltage (i load = 1.6 ma) pa7Cpa0, pb7/sckCpb5/sdo, pc7/v rh Cpc0, pd5, tcmp v ol 0.4 v input high voltage pa7Cpa0, pb7/sckCpb5/sdo, pc7/v rh Cpc0, pd5, pd7/tcap, irq/v pp , reset, osc1 v ih 0.7 v dd v dd v input low voltage pa7Cpa0, pb7/sckCpb5/sdo, pc7/v rh Cpc0, pd5, pd7/tcap, irq/v pp , reset, osc1 v il v ss 0.2 v dd v supply current (3) (4) (5) (6) run mode wait mode (adc on) wait mode (adc off) stop mode 25 c 0 to 70 c (standard) C40 to 125 c i dd 4.7 2.1 1.3 2 6.5 2.9 1.9 30 50 100 ma ma ma m a m a m a i/o ports hi-z leakage current pa7Cpa0, pb7/sckCpb5/sdo, pc7/v rh Cpc0, pd5 i il 10 m a adc ports hi-z leakage current i oz 1 m a input current reset, irq/v pp , osc1, pd7/tcap i in 1 m a capacitance ports (as inputs or outputs) reset, irq/v pp c out c in 12 8 pf programming voltage v pp 16.25 16.5 16.75 v programming current i pp 5 10 ma programming time per byte t epgm 4ms 5-mc68hc705p9 speci?cations 3.3 v dc electrical characteristics 136 specifications motorola 3.3 v dc electrical characteristics 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h unless otherwise noted 2. typical values at midpoint of voltage range, 25 c only 3. run mode and wait mode i dd measured using external square wave clock source (f osc = 2.1 mhz); all inputs 0.2 v from rail; no dc loads; less than 50 pf on all outputs; c l = 20 pf on osc2 4. wait mode and stop mode i dd measured with all ports configured as inputs; v il = 0.2 v; v ih = v dd C 0.2 v 5. stop mode i dd measured with osc1 = v ss 6. wait mode i dd affected linearly by osc2 capacitance table 5. dc electrical characteristics (v dd = 3.3 vdc) (1) characteristic symbol min typ (2) max unit output voltage (i load 10.0 m a) v ol v oh v dd C 0.1 0.1 v output high voltage (i load = C0.2 ma) pa7Cpa0, pb7/sckCpb5/sdo, pc7/v rh Cpc0, pd5, tcmp v oh v dd C 0.3 v output low voltage (i load = 0.4 ma) pa7Cpa0, pb7/sckCpb5/sdo, pc7/v rh Cpc0, pd5, tcmp v ol 0.3 v input high voltage pa7Cpa0, pb7/sckCpb5/sdo, pc7/v rh Cpc0, pd5, pd7/tcap, irq/v pp , reset, osc1 v ih 0.7 v dd v dd v input low voltage pa7Cpa0, pb7/sckCpb5/sdo, pc7/v rh Cpc0, pd5, pd7/tcap, irq/v pp , reset, osc1 v il v ss 0.2 v dd v data-retention mode supply voltage v rm 2.0 v supply current (3) (4) (5) (6) run mode wait mode (adc on) wait mode (adc off) stop mode 25 c 0 to 70 c (standard) C40 to 125 c i dd 1.6 0.9 0.4 1.0 2.3 1.3 0.6 20 40 50 ma ma ma m a m a m a i/o ports hi-z leakage current pa7Cpa0, pb7/sckCpb5/sdo, pc7/v rh Cpc0, pd5 i il 10 m a input current reset, irq/v pp , osc1, pd7/tcap i in 1 m a capacitance ports (as inputs or outputs) reset, irq/v pp c out c in 12 8 pf 6-mc68hc705p9 specifications driver characteristics motorola specifications 137 driver characteristics figure 1. typical high-side driver characteristics figure 2. typical low-side driver characteristics 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 C1.0 C2.0 C3.0 C4.0 C5.0 i oh (ma) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 v dd C v oh (v) 0 C1.0 C2.0 C3.0 C4.0 C5.0 i oh (ma) v dd C v oh (v) notes: 1. shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances. within the limited range of values shown, v vs i curves are approximately straight lines. 2. at v dd = 5.0 v, devices are speci?ed and tested for v ol 800 mv @ i ol = C0.8 ma. 3. at v dd = 3.3 v, devices are speci?ed and tested for v ol 300 mv @ i ol = C0.2 ma. (note 3) (note 2) v dd = 5.0 v v dd = 3.3 v 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 0 2.0 4.0 6.0 8.0 10.0 i ol (ma) 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 v ol (v) 0 2.0 4.0 6.0 8.0 10.0 i ol (ma) (note 3) (note 2) v dd = 5.0 v v dd = 3.3 v v ol (v) notes: 1. shaded area indicates variation in driver characteristics due to changes in temperature and for normal processing tolerances. within the limited range of values shown, v vs i curves are approximately straight lines. 2. at v dd = 5.0 v, devices are speci?ed and tested for v ol 400 mv @ i ol = 1.6 ma. 3. at v dd = 3.3 v, devices are speci?ed and tested for v ol 300 mv @ i ol = 0.4 ma. 7-mc68hc705p9 speci?cations typical supply current vs. internal clock frequency 138 specifications motorola typical supply current vs. internal clock frequency figure 3. typical supply current vs. internal clock frequency 2.0 0 1.0 2.0 3.0 4.0 5.0 0 1.0 1.5 0.5 internal clock frequency (mhz) supply current (ma) 5.5 v 4.5 v 3.6 v 3.0 v run mode 2.0 0.5 1.0 1.5 2.0 0 1.0 1.5 0.5 supply current (ma) 0 0.2 0.4 0.8 1.0 1.2 supply current (ma) 5.5 v 4.5 v 3.6 v 3.0 v run mode 2.0 0 1.0 1.5 0.5 0.6 0 25 c adc on 5.5 v 4.5 v 3.6 v 3.0 v wait mode 25 c adc off internal clock frequency (mhz) internal clock frequency (mhz) 25 c 8-mc68hc705p9 specifications maximum supply current vs. internal clock frequency motorola specifications 139 maximum supply current vs. internal clock frequency figure 4. maximum supply current vs. internal clock frequency supply current (ma) 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 run mode wait mode (adc on) wait mode (adc off) v dd = 5 v 10% C40 to +125 c 2.0 0 1.0 1.5 0.5 internal clock frequency (mhz) 0 0.5 1.0 1.5 2.0 2.5 2.0 0 1.0 1.5 0.5 internal clock frequency (mhz) supply current (ma) run mode wait mode (adc on) wait mode (adc off) v dd = 3.3 v 10% C40 to +125 c 9-mc68hc705p9 speci?cations 5.0 v control timing 140 specifications motorola 5.0 v control timing 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h unless otherwise noted 2. a 2-bit prescaler in the timer is the limiting factor as it counts 4 t cyc 3. the minimum t tltl should not be less than the number of interrupt service routine cycles plus 19 t cyc 4. the minimum t ilil should not be less than the number of interrupt service routine cycles plus 19 t cyc table 6. control timing (v dd = 5.0 vdc) (1) characteristic symbol min max unit oscillator frequency crystal external clock f osc dc 4.2 4.2 mhz internal operating frequency (f osc ? 2) crystal external clock f op dc 2.1 2.1 mhz cycle time (1 ? f op )t cyc 480 ns crystal oscillator startup time t oxov 100 ms stop recovery startup time (crystal oscillator) t ilch 100 ms reset pulse width t rl 1.5 t cyc timer resolution (2) input capture pulse width input capture pulse period t resl t h , t l t tltl 4.0 125 note (3) t cyc ns t cyc interrupt pulse width low (edge-triggered) t ilih 125 ns interrupt pulse period t ilil note (4) t cyc osc1 pulse width t oh , t ol 90 ns rc oscillator stabilization time t rcon 5 m s adc on current stabilization time t adon 100 m s 10-mc68hc705p9 specifications 3.3 v control timing motorola specifications 141 3.3 v control timing 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h unless otherwise noted 2. a 2-bit prescaler in the timer is the limiting factor as it counts 4 t cyc 3. the minimum t tltl should not be less than the number of interrupt service routine cycles plus 19 t cyc 4. the minimum t ilil should not be less than the number of interrupt service routine cycles plus 19 t cyc table 7. control timing (v dd = 3.3 vdc) (1) characteristic symbol min max unit oscillator frequency crystal external clock f osc dc 2.0 2.0 mhz internal operating frequency (f osc ? 2) crystal external clock f op dc 1.0 1.0 mhz cycle time (1 ? f op )t cyc 1ms crystal oscillator startup time t oxov 100 ms stop recovery startup time (crystal oscillator) t ilch 100 ms reset pulse width t rl 1.5 t cyc timer resolution (2) input capture pulse width input capture pulse period t resl t h , t l t tltl 4.0 250 note (3) t cyc ns t cyc interrupt pulse width low (edge-triggered) t ilih 250 ns interrupt pulse period t ilil note (4) t cyc osc1 pulse width t oh , t ol 200 ns 11-mc68hc705p9 speci?cations test load 142 specifications motorola test load figure 5. test load mechanical specifications the mc68hc705p9 is available in the following packages: ? 710 plastic dual in-line package (pdip) ? 733 ceramic dual in-line package (cerdip) ? 751f small outline integrated circuit (soic) the following figures show the latest packages at the time of this publication. to make sure that you have the latest package specifications, contact one of the following: ? local motorola sales office ? motorola mfax C phone 602-244-6609 C email rmfax0@email.sps.mot.com ? worldwide web (wwweb) at http://design-net.com follow mfax or wwweb on-line instructions to retrieve the current mechanical specifications. v dd c r2 r1 test point pins pa7Cpa0 pb7/sckCpb5/sdo pc7/v rh Cpc0 r1 3.26 k w r2 2.38 k w ? c 50 pf 12-mc68hc705p9 specifications mechanical specifications motorola specifications 143 28-pin pdip case #710 28-pin cerdip case #733 ! ! ! #! %% ! $" ! ! ! ! ! ! ! ! # ! " 114 15 28 b a c n k m j d f hg l notes: 1. dimensions a and b includes meniscus. 2. dimension l to center of leads when formed parallel. 3. dimensioning and tolerancing per ansi y14.5m, 1982. 4. controlling dimension: inch. min min max max inches millimeters dim a b c d f g j k l m n 37.84 15.36 5.84 0.55 1.65 0.30 4.06 15 1.27 2.54 bsc 15.24 bsc 36.45 12.70 4.06 0.38 1.27 0.20 3.18 0 0.51 1.435 0.500 0.160 0.015 0.050 0.008 0.125 0 0.020 1.490 0.605 0.230 0.022 0.065 0.012 0.160 15 0.050 0.100 bsc 0.600 bsc 28 15 114 c g h j m b l k f d 28 pl -a- seating plane -t- n 0.25 (0.010) a t m m 13-mc68hc705p9 speci?cations mechanical speci?cations 144 specifications motorola 28-pin soic case #751f ! ! % ! ! ! " ! " $" ! " ! " ! " # ! " ! ! $ ! $" ! ! -a- -b- 114 15 28 -t- c m j -t- k 26x g 28x d 14x p r x 45 f ! 14-mc68hc705p9 motorola index 145 index a accumulator (a) . . . . . . . . . . . . . . . . . .40, 43 adc . . . . . . . . . . . . . . . . . . . . . . . . . .79, 121 adc (analog-to-digital converter) block diagram . . . . . . . . . . . . . . . . . . .122 features . . . . . . . . . . . . . . . . . . . . . . . .121 i/o register summary . . . . . . . . . . . . .123 i/o registers . . . . . . . . . . . . . . . . . . . .126 low-power modes . . . . . . . . . . . . . . . .130 adc data register (addr) . . . . . . . . .124 , 126C127 , 129 adc status and control register (adscr) . . . . . . . . . . . . . . . .124 , 126 addressing modes . . . . . . . . . . . . . . . . . . .40 adon bit . . . . . . . . . . . . . . . . . . . . .127 , 130 adrc bit . . . . . . . . . . . . . . . . .124, 127, 130 alternate timer registers (atrh/l) . . . . . .103 alu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 an[3:0] bits . . . . . . . . . . . . . . . . . . . . . . . . .79 analog-to-digital converter . . . . . . . . . . . .121 arithmetic/logic unit (alu) . . . . . . . . . . . . .36 b bootloader rom . . . . . . . . . . . . . . . . . . . . .26 bootload procedure . . . . . . . . . . . . . . . .29 bootloader circuit . . . . . . . . . . . . . . . . . .28 location . . . . . . . . . . . . . . . . . . . . . . . . .27 brownout . . . . . . . . . . . . . . . . . . . . . . . .58, 86 bypass capacitors . . . . . . . . . . . . . . . . . . . .15 c c bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 case outlines . . . . . . . . . . . . . . .12, 143C144 ccf bit . . . . . . . . . . . . . . . . . . . . . . .124, 12 6 central processor unit . . . . . . . . . . . . . . . . .33 ceramic resonator circuit . . . . . . . . . . . . . .16 ch[2:0] bits . . . . . . . . . . . . . . . . . . . . . . .128 computer operating properly watchdog . . . . . . . . . . . . . . . . . . . . .85 condition code register (ccr) . . .36, 46, 59, 61C62, 102C105 cop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 cop register (copr) . . . . . . . . . . . . .58, 87 cop watchdog cop in stop mode . . . . . . . . . . . . . . . .88 cop in wait mode . . . . . . . . . . . . . . . . .88 cop register (copr) . . . . . . . . . . . . . .87 enabling and disabling . . . . . . . . . . . . .32 features . . . . . . . . . . . . . . . . . . . . . . . . .85 operation . . . . . . . . . . . . . . . . . . . . . . . .86 timeout period . . . . . . . . . . . . . . . . . . . .86 cop watchdog reset . . . . . . . . . . .58, 86C87 copc bit . . . . . . . . . . . . . . . . . . . .58, 87C88 cope bit . . . . . . . . . . . . . . . . . . . . . . . . . .32 cpu . . . . . . . . . . . . . . . . . . . . . . . . . . .33C34 block diagram . . . . . . . . . . . . . . . . . . . .35 control unit . . . . . . . . . . . . . . . . . . .34, 36 features . . . . . . . . . . . . . . . . . . . . . . . . .34 instruction set summary . . . . . . . . . . . .48 index 146 index motorola instruction types . . . . . . . . . . . . . . . . . .43 instructions set . . . . . . . . . . . . . . . . . . .40 opcode map . . . . . . . . . . . . . . . . . . . . .54 registers . . . . . . . . . . . . . . . . . . . . . . . .36 cpu registers . . . . . . . . . . .24, 40, 43, 47, 62 accumulator (a) . . . . . . . . . . . . . . . .40, 43 condition code register (ccr) .36, 46, 59, 61C62, 102C105 index register (x) . . . . . . . . . . . . . . .40C43 program counter (pc) . . . . .42, 45, 56, 62 stack pointer (sp) . . . . . . . . . . . . . . . . .24 crystal at-cut . . . . . . . . . . . . . . . . . . . . . . . . . .16 strip . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 tuning fork . . . . . . . . . . . . . . . . . . . . . . .16 crystal oscillator circuit . . . . . . . . . . . . . . . .16 d data direction registers . . . . . . .111C112, 116 data direction register a (ddra) . .17, 74 data direction register b (ddrb) . .17, 77 data direction register c (ddrc) . .17, 80 data direction register d (ddrd) . .18, 83 data-retention mode . . . . . . . . . . . . . . . . . .70 dcol bit . . . . . . . . . . . . . . . . . . . . . . . . . .119 ddra[7:0] bits . . . . . . . . . . . . . . . . . . . . . .74 ddrb[7:5] bits . . . . . . . . . . . . . . . . . . . . . .77 ddrc[7:0] bits . . . . . . . . . . . . . . . . . . . . . .80 ddrd5 bit . . . . . . . . . . . . . . . . . . . . . . . . .83 e electrical specifications . . . . . . . . . . . . . . .131 control timing . . . . . . . . . . . . . . . .140C141 current versus internal clock frequency . . . . . . . . . . . . .138C139 dc electrical characteristics . . . .135C136 driver characteristics . . . . . . . . . . . . . .137 maximum ratings . . . . . . . . . . . . . . . . .132 operating temperature range . . . . . . .133 power considerations . . . . . . . . . . . . .134 test load . . . . . . . . . . . . . . . . . . . . . . .142 thermal characteristics . . . . . . . . . . . .133 electrostatic damage . . . . . . . . . . . . . . . . .72 epgm bit . . . . . . . . . . . . . . . . . . . . . . . . . .26 eprom erasure . . . . . . . . . . . . . . . . . .25, 30 eprom programming register (eprog) . . . . . . . . . . . . . . . . . . . . .26 eprom/otprom bootloader circuit . . . . . . . . . . . . . . . . .28 eprom erasing . . . . . . . . . . . . . . . . . .30 locations . . . . . . . . . . . . . . . . . . . . . . . .25 programming . . . . . . . . . . . . . . . . . . . .26 external interrupt . . . . . . .17, 59C60, 88, 106 external interrupt vector . . . . . . . . . . . . . . .62 external reset . . . . . . . . . . . . . . . .57, 88, 106 f features . . . . . . . . . . . . . . . . . . . . . . . . . . .10 i i bit . . . . . . . . . . . . . . . . .59, 61C62, 102C105 i/o bits adon bit . . . . . . . . . . . . . . . . . .127, 130 adrc bit . . . . . . . . . . . . . . .124, 127, 130 an[3:0] bits . . . . . . . . . . . . . . . . . . . . . .79 c bit . . . . . . . . . . . . . . . . . . . . . . . . . . .46 ccf bit . . . . . . . . . . . . . . . . . . . .124, 126 ch[2:0] bits . . . . . . . . . . . . . . . . . . . . .128 copc bit . . . . . . . . . . . . . . . . .58, 87C88 cope bit . . . . . . . . . . . . . . . . . . . . . . . .32 dcol bit . . . . . . . . . . . . . . . . . . . . . . .119 ddra[7:0] bits . . . . . . . . . . . . . . . . . . .74 ddrb[7:5] bits . . . . . . . . . . . . . . . . . . .77 ddrc[7:0] bits . . . . . . . . . . . . . . . . . . .80 ddrd5 bit . . . . . . . . . . . . . . . . . . . . . .83 epgm bit . . . . . . . . . . . . . . . . . . . . . . .26 i bit . . . . . . . . . . . . . .59, 61C62, 102C105 icf bit . . . . . . . . . . .61, 98, 101, 104, 106 icie bit . . . . . . . . . . . . . . . . . . .61, 98C99 iedg bit . . . . . . . . . . . . . . . . . . . . . . .100 index motorola index 147 irq bit . . . . . . . . . . . . . . . . . . . . . . . . . .31 latch bit . . . . . . . . . . . . . . . . . . . . . . .26 mstr bit . . . . . . . . . . . . . . . . . . . . . . .117 ocf bit . . . . . . . . . . . . . .61, 98, 101, 105 ocie bit . . . . . . . . . . . . . . . . . .61, 98C99 olvl bit . . . . . . . . . . . . . . . . . . . .94, 100 pa[7:0] bits . . . . . . . . . . . . . . . . . . . . . .73 pb[7:5] bits . . . . . . . . . . . . . . . . . . . . . .76 pc[7:0] bits . . . . . . . . . . . . . . . . . . . . . .79 pd5 bit . . . . . . . . . . . . . . . . . . . . . . . . .82 pd7 bit . . . . . . . . . . . . . . . . . . . . . . . . .82 siop bit . . . . . . . . . . . . . . . . . . . . . . . . .31 spe bit . . . . . . . . . . . .111C112, 116, 119 spif bit . . . . . . . . . . . . . . . . . . . . . . . .118 tof bit . . . . . . . . . . . . . .62, 98, 101C103 toie bit . . . . . . . . . . . . . . . . . . .62, 98C99 i/o pins irq/v pp pin . . . . . . .12, 17, 26C27, 31, 59 osc1 pin . . . . . . . . . . . . . . . . . . . . . . .15 osc2 pin . . . . . . . . . . . . . . . . . . . . . . .15 pb5/sdo pin . . . . . . . . .77, 111C112, 116 pb6/sdi pin . . . . . . . . .77, 111, 113, 116 pb7/sck pin . . . . . . . . .7 6, 111C112, 116 pc3/an0 pin . . . . . . . . . . . . . . . . . . . .128 pc3/an3 pin . . . . . . . . . . . . . . . . .79, 123 pc4/an2 pin . . . . . . . . . . . . .79, 123, 128 pc5/an1 pin . . . . . . . . . . . . .79, 123, 128 pc6/an0 pin . . . . . . . . . . . . . 79, 123, 128 pc7/v rh pin . . . . . . . . . . . . . . . . .79, 123 pd7/tcap pin . . . . . .27, 82, 93, 100C101 reset pin . . . . . . . . . . . . . 17, 27, 56C58 tcmp pin . . . . . . . . . 18, 93C94, 100, 105 v ss pin . . . . . . . . . . . . . . . . . . . . . . . . . .15 i/o port pin termination . . . . . . . . . . . . . . . .72 i/o registers adc data register (addr) . . . . . . . 124, 126C127, 129 adc status and control register (adscr) . . . . . . . . . . . . .124, 126 alternate timer registers (atrh/l) . . .103 cop register (copr) . . . . . . . . . . .58, 87 data direction register a (ddra) . . . . .74 data direction register b (ddrb) . . . . .77 data direction register c (ddrc) . . . . .80 data direction register d (ddrd) . . . . .83 eprom programming register (eprog) . . . . . . . . . . . . . . . . . .26 input capture registers (icrh/icrl) . . . . . . . . . . . . . . . .93 input capture registers (icrh/l) . . . . . .100C101, 104, 106 mask option register (mor) . . . . . . . . . . .12, 25, 31, 86 output compare registers (ocrh/l) . . . . . . . . .100C101, 105 output compare registers (ocrh/ocrl) . . . . . . . . . . . . . .94 port a data register (porta) . . . . . . . .73 port b data register (portb) . . . . . . . .76 port c data register (portc) . . . . . . . .79 port d data register (portd) . . . . . . . .82 siop control register (scr) . . . . . . . . . . . .111, 116, 119 siop data register (sdr) . . . . . .118C119 siop status register (ssr) . . . . . . . . .118 timer control register (tcr) . . .61C62, 99 timer registers (trh/l) . . . . . . . .100C102 timer status register (tsr) . . . . . .61C62, 100, 104C105 icf bit . . . . . . . . . . . . .61, 98, 101, 104, 106 icie bit . . . . . . . . . . . . . . . . . . . . . .61, 98C99 iedg bit . . . . . . . . . . . . . . . . . . . . . . . . . .100 index register (x) . . . . . . . . . . . . . . . . .40C43 input capture interrupt . . . . . . . . . . . . . . . .90 input capture registers (icrh/l) . . . . .93, 100C101, 104, 106 instruction set . . . . . . . . . . . . . . . . . . . . . . .40 addressing modes . . . . . . . . . . . . . . . .40 instruction set summary . . . . . . . . . . . .48 instruction types . . . . . . . . . . . . . . . . . .43 opcode map . . . . . . . . . . . . . . . . . . . . .54 internal clock . . . . . . . . . . . . . . . . . . . . . . .86 frequency . . . . . . . . . . . . . . . . . . . . . . .15 index 148 index motorola internal rc oscillator . . . . . . . . . . . .124, 127 interrupts . . . . . . . . . . . . . . . . . . . . . . .55, 98 external interrupt . . . . . . . . . . . . . . . . . .59 external interrupt logic . . . . . . . . . . . . . .60 external interrupt timing . . . . . . . . .60C61 interrupt flowchart . . . . . . . . . . . . . . . . .64 interrupt processing . . . . . . . . . . . . . . .62 interrupt sources . . . . . . . . . . . . . . . . . .59 interrupt stacking order . . . . . . . . . . . . .63 reset/interrupt vector addresses . . . . . .63 software interrupt . . . . . . . . . . . . . . . . .59 timer interrupts . . . . . . . . . . . . . . . . . . .61 introduction, mc68hc705p9 . . . . . . . . . . . .9 irq bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 irq latch . . . . . . . . . . . . . . . . . . . . . . . . . .59 irq/v pp pin . . . . . . . . . .12, 17, 26C27, 31, 59 j junction temperature . . . . . . . . . . . . . . . . .134 l latch bit . . . . . . . . . . . . . . . . . . . . . . . . . .26 literature updates . . . . . . . . . . . . . . . . . . .151 low voltage protection . . . . . . . . . . . . . . . . .58 low-power modes . . . . . . . . . . . . . . . . . . . .65 adc in stop and wait modes . . . . . . . .130 cop in stop and wait modes . . . . . . . .88 data-retention mode . . . . . . . . . . . . . . .70 siop in stop and wait modes . . . . . . .120 stop instruction flowchart . . . . . . . . . .67 stop mode . . . . . . . . . . . . . . . . . . . . . . .65 stop recovery timing . . . . . . . . . . . . . . .66 stop/wait clock logic . . . . . . . . . . . . .70 timer in stop and wait modes . . . . . . .106 wait instruction flowchart . . . . . . . . . .69 wait mode . . . . . . . . . . . . . . . . . . . . . . .68 m mask option register (mor) . . . 12, 25, 31, 86 mechanical specifications packages . . . . . . . . . . . . . . . . . . . . . . .142 memory . . . . . . . . . . . . . . . . . . . . . . . . . . .19 eprom/otprom . . . . . . . . . . . . . . . .25 features . . . . . . . . . . . . . . . . . . . . . . . . .19 parallel i/o register summary . . . . . . . .21 ram . . . . . . . . . . . . . . . . . . . . . . . . . . .24 mstr bit . . . . . . . . . . . . . . . . . . . . . . . . .117 n noise . . . . . . . . . . . . . . . . . . . . . . . . . .15, 17 o ocf bit . . . . . . . . . . . . . . . . .61, 98, 101, 105 ocie bit . . . . . . . . . . . . . . . . . . . . .61, 98C99 olvl bit . . . . . . . . . . . . . . . . . . . . . . .94, 100 on-chip oscillator . . . . . . . . . . . . . . . . . . . .15 frequency . . . . . . . . . . . . . . . . . . . . . . .15 stabilization delay . . . . . . . . . .56, 88, 120 opcode map . . . . . . . . . . . . . . . . . . . . . . . .54 operating temperature . . . . . . . . . . . . . . . .12 operating temperature range . . . . . . . . . .133 options programmable . . . . . . . . . . . . . . . . . . .12 order numbers . . . . . . . . . . . . . . . . . . . . . .12 osc1 pin . . . . . . . . . . . . . . . . . . . . . . . . . .15 osc2 pin . . . . . . . . . . . . . . . . . . . . . . . . . .15 output compare interrupt . . . . . . . . . . .90, 94 output compare registers (ocrh/l) . . . . . . . .94, 100C101, 105 p pa[7:0] bits . . . . . . . . . . . . . . . . . . . . . . . . .73 package dimensions cerdip . . . . . . . . . . . . . . . . . . . . . . . . .143 pdip . . . . . . . . . . . . . . . . . . . . . . . . . .143 soic . . . . . . . . . . . . . . . . . . . . . . . . . .144 package types . . . . . . . . . . . . . . . . . . . . . .12 parallel i/o ports . . . . . . . . . . . . . . . . . . . . .71 pb[7:5] bits . . . . . . . . . . . . . . . . . . . . . . . . .76 pb5/sdo pin . . . . . . . . . . .77, 111C112, 116 index motorola index 149 pb6/sdi pin . . . . . . . . . . . .77, 111, 113, 116 pb7/sck pin . . . . . . . . . . .76, 111C112, 116 pb7sck pin . . . . . . . . . . . . . . . . . . . . . . .111 pc[7:0] bits . . . . . . . . . . . . . . . . . . . . . . . . .79 pc3/an3 pin . . . . . . . . . . . . . . . .79, 123, 128 pc4/an2 pin . . . . . . . . . . . . . . . .79, 123, 128 pc5/an1 pin . . . . . . . . . . . . . . . .79, 123, 128 pc6/an0 pin . . . . . . . . . . . . . . . .79, 123, 128 pc7/v rh pin . . . . . . . . . . . . . . . . . . . .79, 123 pd5 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 pd7 bit . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 pd7/tcap pin . . . . . . . .27, 82, 93, 100C101 pin assignments . . . . . . . . . . . . . . . . . . . . .14 pin descriptions . . . . . . . . . . . . . . . . . . . . .13 pin functions . . . . . . . . . . . . . . . . . . . . . . . .15 port a . . . . . . . . . . . . . . . . . . . . . . . . . .17, 73 data direction register a (ddra) . . . . .74 port a data register (porta) . . . . . . . .73 port b . . . . . . . . . . . . . . . . . . . . . . . . . .17, 76 data direction register b (ddrb) . . . . .77 port b data register (portb) . . . . . . . .76 port c . . . . . . . . . . . . . . . . . . . . . . . . . .17, 79 data direction register c (ddrc) . . . . .80 port c data register (portc) . . . . . . . .79 port d . . . . . . . . . . . . . . . . . . . . . . . . . .18, 82 data direction register d (ddrd) . . . . .83 port d data register (portd) . . . . . . . .82 ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 parallel i/o port register summary . . . . .72 port a . . . . . . . . . . . . . . . . . . . . . . . . . .73 port b . . . . . . . . . . . . . . . . . . . . . . . . . .76 port c . . . . . . . . . . . . . . . . . . . . . . . . . .79 port d . . . . . . . . . . . . . . . . . . . . . . . . . .82 power dissipation . . . . . . . . . . . . . . .128, 134 power supply (v dd ) . . . . . . . . . . . . . . . .15, 30 power supply (v pp ) . . . . . . . . . . . . . . . . . . .29 power-on reset . . . . . . . . . . . . . . . . . . . . . .56 program counter (pc) . . . . . . . .42, 45, 56, 62 programmable options cop watchdog enable/disable . . . .12, 86 external interrupt pin triggering . . . .12, 31 siop data format . . . . . . . . . . . . .12, 110 q quartz window . . . . . . . . . . . . . . . . . . . . . .25 r ram locations . . . . . . . . . . . . . . . . . . . . . . . .24 stack . . . . . . . . . . . . . . . . . . . . . . . . . . .24 reading . . . . . . . . . . . . . . . . . . . . . . . . . .102 registers adc i/o register summary . . . . . . . . .123 cpu registers . . . . . . . . . . . . . . . . . . . .36 parallel i/o port register summary . . . .72 parallel i/o register summary . . . . . . . .21 siop i/o register summary . . . . . . . . .109 timer i/o register summary . . . . . . . . . .92 reset pin . . . . . . . . . . . . . . . .17, 27, 56C58 reset sources cop watchdog . . . . . . . . . . . . . . . . . . .56 power-on . . . . . . . . . . . . . . . . . . . . . . . .56 reset pin . . . . . . . . . . . . . . . . . . . . . .56 reset vector . . . . . . . . . . . . . . . . . . . . . . . .56 resets . . . . . . . . . . . . . . . . . . . . . . . . . .55C56 cop watchdog reset . . . . . . . . . . .58, 86 cop watchdog reset operation . . . . . .86 external reset . . . . . . . . . . . . . . . . . . . .57 external reset timing . . . . . . . . . . . . . . .57 low-voltage protection reset . . . . . . . . .58 power-on reset (por) . . . . . . . . . . . . .56 power-on reset (por) timing . . . . . . . .57 reset sources . . . . . . . . . . . . . . . . . . . .56 reset/interrupt vector addresses . . . . . .63 resets and interrupts . . . . . . . . . . . . . . . . .55 s serial input/output port . . . . . . . . . . . . . . .107 siop . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 index 150 index motorola siop (serial input/output port) block diagram . . . . . . . . . . . . . . . . . . .109 description . . . . . . . . . . . . . . . . . . . . . .108 features . . . . . . . . . . . . . . . . . . . . . . . .108 i/o register summary . . . . . . . . . . . . .109 i/o registers . . . . . . . . . . . . . . . . . . . .116 low-power modes . . . . . . . . . . . . . . . .120 operation . . . . . . . . . . . . . . . . . . . . . . .110 timing . . . . . . . . . . . . . . . . . . . . .114C115 siop bit . . . . . . . . . . . . . . . . . . . . . . . . . . .31 siop control register (scr) . . .111, 116, 119 siop data register (sdr) . . . . . . . . .118C119 siop status register (ssr) . . . . . . . . . . .118 software failure . . . . . . . . . . . . . . . . . . . . . .86 software interrupt vector . . . . . . . . . . . . . . .62 spe bit . . . . . . . . . . . . . . .111C112, 116, 119 specifications . . . . . . . . . . . . . . . . . . . . . .131 see "electrical specifications." . . . . . .132 see "mechanical specifications." . . . .142 spif bit . . . . . . . . . . . . . . . . . . . . . . . . . . .118 stack pointer (sp) . . . . . . . . . . . . . . . . . . . .24 stack ram . . . . . . . . . . . . . . . . . . . . . .24, 62 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . .65 effect on adc . . . . . . . . . . . . . . . . . . .130 effect on capture/compare timer . . . . .106 effect on cop watchdog . . . . . . . . . . . .88 effect on siop . . . . . . . . . . . . . . . . . . .120 stop instruction flowchart . . . . . . . . . .67 stop recovery timing . . . . . . . . . . . . . . .66 stop/wait clock logic . . . . . . . . . . . . .70 supply voltage (v dd ) . . . . . . . . . . . . . .86, 132 t tcmp pin . . . . . . . . . . . .18, 93C94, 100, 105 thermal resistance . . . . . . . . . . . . . .133C134 timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 block diagram . . . . . . . . . . . . . . . . . . . .91 features . . . . . . . . . . . . . . . . . . . . . . . . .90 i/o register summary . . . . . . . . . . . . . .92 i/o registers . . . . . . . . . . . . . . . . . . . . .98 interrupts . . . . . . . . . . . . . . . . . . . . .61, 98 low-power modes . . . . . . . . . . . . . . . .106 operation . . . . . . . . . . . . . . . . . . . . . . . .93 reading . . . . . . . . . . . . . . . . . . . . .93, 103 timing . . . . . . . . . . . . . . . . . . . . . . .95C97 timer control register (tcr) . . . . . .61C62, 99 timer interrupt vector . . . . . . . . . . . . . . . . .62 timer registers (trh/l) . . . . . . . . . . .100C102 timer resolution . . . . . . . . . . . . . . . . . . . . .93 timer status register (tsr) . . . . . . . . .61C62, 100, 104C105 tof bit . . . . . . . . . . . . . . . . .62, 98, 101C103 toie bit . . . . . . . . . . . . . . . . . . . . .62, 98C99 v v dd power supply . . . . . . . . . . . . . . . . .15, 30 v pp power supply . . . . . . . . . . . . . . . . . . . .29 v ss pin . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 w wait mode . . . . . . . . . . . . . . . . . . . . . . . . . .68 effect on adc . . . . . . . . . . . . . . . . . . .130 effect on capture/compare timer . . . . .106 effect on cop watchdog . . . . . . . . . . . .88 effect on siop . . . . . . . . . . . . . . . . . .120 stop/wait clock logic . . . . . . . . . . . .70 wait instruction flowchart . . . . . . . . . .69 motorola literature updates 151 literature updates this document contains the latest data available at publication time. for updates, contact one of the following: literature distribution centers call or order literature by mail. usa/europe: motorola literature distribution p.o. box 20912 phoenix, arizona 85036 phone 1 800 441-2447 or 602 303-5454 japan: nippon motorola ltd. tatsumi-spd-jldc toshikatsu otsuki 6f seibu-butsuryu center 3-14-2 tatsumi koto-ku tokyo 135, japan phone 03-3521-8315 hong kong: motorola semiconductors h.k. ltd. 8b tai ping industrial park 51 ting kok road tai po, n.t., hong kong phone 852-26629298 literature updates mfax mc68hc705p9 152 literature updates motorola mfax call to access this worldwide faxing service. rmfax0@email.sps.mot.com touch-tone 602 244-6609 or, on the http://design-net.com home page, select the mfax icon. obtain a fax of complete, easy-to-use mfax instructions by entering your fax number and then pressing the 1 key. motorola sps world marketing world wide web server use the internet to access this world wide web server. use the following url: http://design-net.com csic microcontroller divisions web site directly access the csic microcontroller divisions web site with the following url: http://design-net.com/csic/csic_home.html mc68hc705p9 rev. 3 technical data book please help us to continue improving the quality and usefulness of our data books by filling out this form and sending your comments to us. you can return the form by mail, or fax it to 512-891-3236. thank you for your help and continued support! 1. how do you rate the quality of this data book? 2. are you able to find the information you need easily? 3. what are your recommendations for making this data book more useful? 4. what additional information would you like to see included in future data books? high low high low organization tables readability table of contents accuracy page size/binding figures overall impression ye s n o first: cut along this line to remove motorola 6501 william cannon drive west mail stop oe17 austin, texas 78735-8598 attention: csic publications department second: fold back along this line please supply the following information (optional). name: __________________________________________________________________ company name: ________________________________________________________ title: ____________________________________________________________________ address: _________________________________________________________________ city: ____________________________________________state: _____zip:__________ phone number: _________________________________________________________ csic microcontroller division usa please paste postage here m o t o r o l a csic microcontrollers mc68hc705p9/d motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and speci?cally disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its of?cers, employees, subsidiaries, af?liates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?rmative action employer. how to reach us: mfax: rmfax0@email.sps.mot.com - touchtone (602) 244-6609 internet: http://design-net.com usa/europe: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036. 1-800-441-2447 japan: nippon motorola ltd.; tatsumi-spd-jldc, toshikatsu otsuki, 6f seibu-butsuryu-center, 3-14-3 tatsumi koto-ku, tokyo 135, japan. 03-3521-8315 hong kong: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting tok road, tai po, n.t., hong kong. 852-26629298 mc68hc705p9/d |
Price & Availability of MC68HC705P9VDW
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |